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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, IPSJ-ARC 2007-05-31
14:15
Kanagawa   A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. ... [more] ICD2007-22
pp.31-35
ICD 2007-04-12
11:10
Oita   [Invited Talk] A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current
Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] ICD2007-5
pp.23-28
ICD 2006-05-25
13:30
Hyogo Kobe University Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs
Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL)
 [more] ICD2006-26
pp.25-30
ICD 2006-04-13
10:10
Oita Oita University An 8.4ns Column-Access 1.6Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme
Shuichi Kubouchi (Hitachi ULSI), Hiroki Fujisawa, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda (Elpida Memory), Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka (Hitachi ULSI), Masayuki Nakamura (Elpida Memory)
The column access time of a 512Mb DDR3 SDRAM made by a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through ... [more] ICD2006-3
pp.13-18
ICD, ITE-CE 2006-01-26
10:30
Tokyo Kikai-Shinko-Kaikan Bldg. Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory
Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas)
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] ICD2005-206
pp.7-12
ICD, CPM 2005-09-09
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
Masaharu Yamamoto (STARC), Yayoi Hayasi, Hitoshi Endo (Hitachi ULSI), Hiroo Masuda (STARC)
 [more] CPM2005-103 ICD2005-113
pp.41-46
ICD 2005-04-14
09:30
Fukuoka   Low-Power Embedded SRAM Modules with Expanded Margins for Writing
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.)
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] ICD2005-2
pp.7-12
ICD 2005-04-15
14:00
Fukuoka   Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi)
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] ICD2005-18
pp.31-36
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