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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPM, ICD 2008-01-18
13:00		 Tokyo Kikai-Shinko-Kaikan Bldg Study on Low Stress Condition of Pseudo-SOC Integration Using Stress Analysis
Yutaka Onozuka, Hiroshi Yamada, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R & D Center) CPM2007-141 ICD2007-152		 The authors have proposed a pseudo-SOC (System on Chip) technology, forming redistribution global layer with semiconduct... [more] CPM2007-141 ICD2007-152
pp.77-82
MW, ED 2007-01-19
15:50		 Tokyo Kikai-Shinko-Kaikan Bldg. High Voltage and High Frequency( over10MHz) Class-E Power-Supplies Using a GaN-HEMT
Wataru Saito (Toshiba Semiconductor), Tomokazu Domon, Kunio Tsuda (Toshiba R & D Center), Ichiro Omura (Toshiba Semiconductor) 		GaN-HEMTs can realize high-voltage and ultra-low on-resistance due to high critical electric field and high electron mob... [more] ED2006-237 MW2006-190
pp.205-208
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