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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPM, ICD |
2008-01-18 14:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg |
Chip Thinning Technologies Realizing High Chip Strength Shinya Takyu, Tetsuya Kurosawa, Noriko Shimizu, Susumu Harada (Toshiba Co.) CPM2007-145 ICD2007-156 |
Accompanying the rapid progress of the digital network information society, there is strong demand for high functionalit... [more] |
CPM2007-145 ICD2007-156 pp.99-103 |
ICD |
2007-04-13 14:20 |
Oita |
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25nm SONOS-type Memory Device usinh Double Tunnel Junction Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba Co.) ICD2007-16 |
When a nano meter scale conductive island is lying between two tunnel resistance, this structure is called "Double junct... [more] |
ICD2007-16 pp.89-93 |
ICD |
2006-04-14 09:55 |
Oita |
Oita University |
High Performance 16Mb MRAM for Portable Applications Yuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Ryosuke Takizawa, Yoshihiro Ueda, Kiyotaro Itagaki, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, Masahiko Nakayama, Hiroaki Yoda (Toshiba Co.) |
[more] |
ICD2006-13 pp.69-73 |
ICD |
2006-04-14 14:20 |
Oita |
Oita University |
Floating Gate Type Planar MOSFET Memory with 35 nm Gate Length using Double Junction Tunneling Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba) |
[more] |
ICD2006-19 pp.103-107 |
MW |
2005-12-16 09:25 |
Hiroshima |
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Development of a High Efficiency OFDM Power Amplifier with a pre-distortion circuit that uses Temperature Compensation in the 7GHz band Kazuhisa Haeiwa (Hiroshima City Univ.), Tohru Abe, Izuru Murasaki (NHK), Tetsuo Yoshida, Jyunichi Togashi (Toshiba Co.) |
We developed a high efficiency power amplifier with a pre-distortion circuit that uses temperature compensation in the I... [more] |
MW2005-129 pp.7-12 |
SIP, ICD, IE, IPSJ-SLDM |
2005-10-20 15:50 |
Miyagi |
Ichinobo, Sakunami-Spa |
DFT Technique for Memory Macro with Built-in ECC Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama (Toshiba Co.) |
DFT techniques to implement ECC circuitry on
memory macro with no additional test cost are
proposed. New methodology t... [more] |
SIP2005-111 ICD2005-130 IE2005-75 pp.95-100 |
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