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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 36  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2024-04-11
14:30
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Lecture] A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing
Kenta Suzuki, Keizo Hiraga, Bessho Kazuhiro (Sony), Kimiyoshi Usami (SIT), Taku Umebayashi (Sony) ICD2024-7
(To be available after the conference date) [more] ICD2024-7
pp.20-23
SDM 2024-02-21
15:50
Tokyo Tokyo University-Hongo-Engineering Bldg.4
(Primary: On-site, Secondary: Online)
[Invited Talk] Recent Studies of WoW and CoW Cu-Cu Hybrid Bonding
Yoshihisa Kagawa, Yukako Ikegami, Takahiro Kamei, Hayato Iwamoto (SSS) SDM2023-87
In recent years, a variety of 3D stacked devices have been proposed. The Cu-Cu hybrid bonding that can realize high dens... [more] SDM2023-87
pp.31-35
AP 2024-02-16
14:00
Mie Sinfonia Technology Hibiki Hall Ise
(Primary: On-site, Secondary: Online)
[Invited Lecture] Energy Harvest of Electromagnetic Wave Noise from near electrical equipment -- Toward the realization of an ecological society --
Yoshitaka Yoshino (SonySS) AP2023-195
While environmental issues are attracting attention for the sustainable development of society, efforts to reduce enviro... [more] AP2023-195
pp.41-45
SDM 2024-01-31
15:20
Tokyo KIT Toranomon Graduate School
(Primary: On-site, Secondary: Online)
[Invited Talk] A highly reliable 1.8 V 1 Mb Hf0.5Zr0.5O2-based 1T1C FeRAM Array with 3-D Capacitors -- Report on IEDM2023 --
Jun Okuno, Takafumi Kunihiro, Yusuke Shuto, Tsubasa Yonai, Ryo Ono (Sony Semiconductor Solutions Corp.), Ruben Alcala (NaMLab), Maximilian Lederer, Konrad Seidel (Fraunhofer IPMS), Thomas Mikolajick, Uwe Schroeder (NaMLab), Taku Umebayashi (Sony Semiconductor Solutions Corp.) SDM2023-79
 [more] SDM2023-79
pp.20-23
RECONF, VLD 2024-01-29
17:00
Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93
As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] VLD2023-90 RECONF2023-93
pp.59-64
RECONF, VLD 2024-01-29
17:25
Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)
Comparison of latch-based circuit and flip-flop-based circuit in actual device
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-91 RECONF2023-94
The comparison results of current consumption, maximum operating frequency (Fmax) characteristics and minimum operating ... [more] VLD2023-91 RECONF2023-94
pp.65-70
LQE, ED, CPM 2023-12-01
09:55
Shizuoka   Simultaneous microscopic PA/PL line-scan measurements in InGaN-quantum wells on a stripe-core GaN Substrate
Syoki Jinno, Atsushi A. Yamaguchi, Keito Mori-Tamamura (Kanazawa Inst. of Tech.), Susumu Kusanagi, Yuya Kanitani, Shigetaka Tomiya, Yoshihiro Kudo (Sony Semiconductor Solutions Corp.) ED2023-25 CPM2023-67 LQE2023-65
Accurate measurement of internal quantum efficiency (IQE) is necessary for a comprehensive understanding of the electron... [more] ED2023-25 CPM2023-67 LQE2023-65
pp.52-55
LQE, ED, CPM 2023-12-01
10:20
Shizuoka   Polarization control of surface emission from c-plane InGaN quantum wells and determination of deformation potential in InGaN alloy materials
Keito Mori-Tamamura, Atsushi A. Yamaguchi (Kanazawa Inst. Tech), Tomohiro Makino, Maho Ohara, Tatsushi Hamaguchi, Rintaro Koda (Sony Semiconductor Solutions) ED2023-26 CPM2023-68 LQE2023-66
InGaN-quantum-well (QW) based vertical-cavity surface-emitting lasers (VCSELs), which are usually fabricated on the c-pl... [more] ED2023-26 CPM2023-68 LQE2023-66
pp.56-59
SDM 2023-11-10
11:20
Tokyo
(Primary: On-site, Secondary: Online)
[Invited Talk] Self-Consistent Monte Carlo Device Simulation of Capture-Excitation Processes of Carriers
Futo Hashimoto, Toma Suzuki, Hideki Minari, Nobuya Nakazaki, Jun Komachi (Sony Semiconductor Solutions), Nobuyuki Sano (Univ. of Tsukuba) SDM2023-69
The capture-excitation processes of carriers are implemented in self-consistent Monte Carlo device simulations. The car... [more] SDM2023-69
pp.31-34
SDM, ICD, ITE-IST [detail] 2023-08-02
10:45
Hokkaido Hokkaido Univ. Multimedia Education Bldg. 3F
(Primary: On-site, Secondary: Online)
[Invited Talk] The Image Sensor Technology: Building the Foundation for Information Sensing Societies
Hayato Wakabayashi (Sony Semiconductor Solutions)
 [more]
HWS, VLD 2023-03-01
11:25
Okinawa
(Primary: On-site, Secondary: Online)
Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test
Daisuke Goeda (KIT), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michihiro Shintani (KIT) VLD2022-74 HWS2022-45
 [more] VLD2022-74 HWS2022-45
pp.7-12
HWS, VLD 2023-03-02
13:25
Okinawa
(Primary: On-site, Secondary: Online)
[Memorial Lecture] Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects
Takuma Nagao (NAIST), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing), Michiko Inoue (NAIST), Michihiro Shintani (Kyoto Institute of Technology) VLD2022-91 HWS2022-62
Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale inte... [more] VLD2022-91 HWS2022-62
p.109
ICD, SDM, ITE-IST [detail] 2022-08-08
09:15
Online   [Invited Talk] A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake (Sony Semiconductor Solutions), Takashi Watanabe, Kunihiko Araki, Naoki Nei (Sony Semiconductor Manufacturing), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (Sony Semiconductor Solutions), Hiroyuki Kawashima, Yusaku Kobayashi (Sony Semiconductor Manufacturing), Tomoyuki Hirano, Keiji Tatani (Sony Semiconductor Solutions) SDM2022-33 ICD2022-1
(To be available after the conference date) [more] SDM2022-33 ICD2022-1
pp.1-6
ICD, SDM, ITE-IST [detail] 2022-08-08
10:00
Online   [Invited Talk] Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors
Naohiko Kimizuka, Shota Kitamura, Akiko Honjo, Koichi Baba, Toshihiro Kurobe, Hideomi Kumano, Takuya Toyohuku (Sony Semiconductor Solutions), Kouhei Takeuchi, Shota Nishimura (Sony Semiconductor Manufacturing), Akihiko Kato, Tomoyuki Hirano, Yusuke Oike (Sony Semiconductor Solutions) SDM2022-34 ICD2022-2
The pixel size of CMOS image sensor (CIS) continues to be rapidly decreasing due to strong demand from mobile applicatio... [more] SDM2022-34 ICD2022-2
p.7
VLD, HWS [detail] 2022-03-08
09:55
Online Online Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment
Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology) VLD2021-92 HWS2021-69
Statistical methods for predicting the performance of large-scale integrated circuits (LSIs) manufactured on a wafer are... [more] VLD2021-92 HWS2021-69
pp.87-92
SDM 2022-02-04
11:20
Online Online [Invited Talk] 3D Sequential Process Integration for CMOS Image Sensor
Keiichi Nakazawa, Junpei Yamamoto, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Shigetaka Mori, Shintaro Okamoto, Akito Shimizu, Koichi Baba, Hidetoshi Onuma, Akira Matsumoto, Koichiro Zaitsu, Keiji Tanani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semiconductor Solutions) SDM2021-77
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] SDM2021-77
pp.13-16
SDM 2022-01-31
16:00
Online Online [Invited Talk] ****
Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintaro Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Koichiro Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semiconductor Solutions) SDM2021-73
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] SDM2021-73
pp.20-23
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-01
10:35
Online Online Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28
pp.19-24
SDM 2021-11-11
16:40
Online Online [Invited Talk] SISPAD2021 Review
Hideki Minari (Sony Semiconductor Solutions) SDM2021-59
2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) was held on September 27-29,... [more] SDM2021-59
pp.33-37
SDM, ICD, ITE-IST [detail] 2021-08-18
09:30
Online Online [Invited Talk] Analog in-memory computing in FeFET based 1T1R array for low-power edge AI applications
Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga (SONY), Yusuke Shuto, Jun Okuno, Kenta Konishi (SSS), Masanori Tsukamoto, Kazunobu Ohkuri (SONY), Taku Umebayashi (SSS), Takayuki Ezaki (SONY) SDM2021-36 ICD2021-7
Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing mass... [more] SDM2021-36 ICD2021-7
pp.33-37
 Results 1 - 20 of 36  /  [Next]  
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