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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2011-04-19 11:45 |
Hyogo | Kobe University Takigawa Memorial Hall | Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo)  ICD2011-13 |
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. ... [more] | ICD2011-13 pp.71-76 |
| DC | 2011-02-14 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Variation Aware Test Methodology Based on Statistical Static Timing Analysis Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62 |
The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to proces... [more] | DC2010-62 pp.21-26 |
| ICD | 2010-12-17 13:50 |
Tokyo | RCAST, Univ. of Tokyo | Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems Yu Pu, Xin Zhang, Jim Huang (Univ. of Tokyo), Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2010-122 |
Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit te... [more] | ICD2010-122 pp.135-140 |
| ICD | 2010-12-17 16:15 |
Tokyo | RCAST, Univ. of Tokyo | A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction Xin Zhang, Yu Pu, Koichi Ishida (Univ. of Tokyo), Yoshikatsu Ryu, Yasuyuki Okuma (STARC), Po-Hung Chen (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) ICD2010-127 |
To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a no... [more] | ICD2010-127 pp.163-167 |
| ICD, SDM | 2010-08-27 13:45 |
Hokkaido | Sapporo Center for Gender Equality | 70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-145 ICD2010-60 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] | SDM2010-145 ICD2010-60 pp.115-120 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | Device-modeling techniques for high-frequency circuits operated at over 100GHz Ryuichi Fujimoto (STARC), Kyoya Takano, Mizuki Motoyoshi (Univ. of Tokyo), Uroschanit Yodprasit, Minoru Fujishima (Hiroshima Univ.) |
Device-modeling techniques for high-frequency circuits operated at over 100 GHz is presented. When the MOSFET model incl... [more] | |
| SDM | 2010-06-22 15:15 |
Tokyo | An401・402 Inst. Indus. Sci., The Univ. of Tokyo | 70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-44 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] | SDM2010-44 pp.61-65 |
| SDM | 2010-02-05 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Defects in Cu/low-k Interconnects Probed Using Monoenergetic Positron Beams Akira Uedono (Tsukuba Univ.), Naoya Inoue, Y. Hayashi, K. Eguchi, T. Nakamura, Y. Hirose, Masaki Yoshimaru (STARC), Nagayasu Oshima, Toshiyuki Ohdaira, R. Suzuki (National Institute of Advanced Industrial Science and Technology) SDM2009-190 |
Defects in SiOCH/Cu damascene structures were probed using monoenergetic positron beams. Doppler broadening spectra of t... [more] | SDM2009-190 pp.49-52 |
| ICD, ITE-IST | 2009-10-01 10:00 |
Tokyo | CIC Tokyo (Tamachi) | Evaluation and Analysis of Substrate Noise in Microprocessor Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35 |
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through... [more] | ICD2009-35 pp.11-14 |
| SDM | 2009-06-19 16:00 |
Tokyo | An401・402 Inst. Indus. Sci., The Univ. of Tokyo | Floating Gate Memory with Biomineralized Nanodots Embedded in High-k Gate Dielectric Kosuke Ohara, Ichiro Yamashita (NAIST), Toshitake Yaegashi, Masahiro Moniwa, Masaki Yoshimaru (STARC), Yukiharu Uraoka (NAIST/CREST) SDM2009-40 |
The memory properties of nano-dot-type floating gate memories with Co bio-nanodots (Co-BNDs) embedded in HfO2 layer were... [more] | SDM2009-40 pp.77-80 |
| DC | 2009-06-19 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Power & Noise Aware Test Utilizing Preliminary Estimation Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo (STARC) DC2009-15 |
Advances in low power design technologies is making issues on power dissipation and IR-drop in testing more serious. Exc... [more] | DC2009-15 pp.29-30 |
| DC | 2009-02-16 14:40 |
Tokyo | Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2008-75 |
[more] | DC2008-75 pp.43-48 |
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| SDM | 2008-06-10 14:35 |
Tokyo | An401・402, Inst. Indus. Sci., The Univ. of Tokyo | Bio-nano dot floating gate memory with High-k films Kosuke Ohara, Yukiharu Uraoka, Takashi Fuyuki, Ichiro Yamashita (NAIST), Toshitake Yaegashi, Masahiro Moniwa, Masaki Yoshimaru (STARC) SDM2008-57 |
The memory characteristics of nanodot floating gate memories with High-k tunnel oxide were investigated using MOS capaci... [more] | SDM2008-57 pp.89-92 |
| SDM | 2006-06-22 10:30 |
Hiroshima | Faculty Club, Hiroshima Univ. | Analysis of nitrogen depth profile in SiO2/SiN stacks studied by angle-resolved photoemission spectroscopy Satoshi Toyoda, Jun Okabayashi, Masaharu Oshima (Tokyo Univ.), Guo-Lin Liu, Ziyuan Liu, Kazuto Ikeda, Koji Usuda (STARC) |
Nitrogen in-depth profile and chemical states in Si oxynitride films are important to understand characteristics of the ... [more] | SDM2006-55 pp.77-80 |
| CAS, NLP | 2005-09-15 15:00 |
Niigata | Nagaoka Univ. of Technology | Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew Zhangcai Huang (Waseda Univ.), Atsushi Kurukawa (STAC), Yasuaki Inoue (Waseda Univ.) |
In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Tim... [more] |
CAS2005-31 NLP2005-44 pp.31-36 |
| ICD, CPM | 2005-09-09 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG Masaharu Yamamoto (STARC), Yayoi Hayasi, Hitoshi Endo (Hitachi ULSI), Hiroo Masuda (STARC) |
[more] | CPM2005-103 ICD2005-113 pp.41-46 |
| ICD, SDM | 2005-08-19 13:25 |
Hokkaido | HAKODATE KOKUSAI HOTEL | 0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process Motoi Ichihashi, Haruki Toda, Yasuo Itoh, Koichiro Ishibashi (STARC) |
Asymmetric Three-Tr. Cell (ATC) DRAM which has one P- and two N-MOS transistors for one unit cell is proposed with "forc... [more] | SDM2005-151 ICD2005-90 pp.49-54 |
| CPSY, VLD, IPSJ-SLDM | 2005-01-25 13:30 |
Kanagawa | [Invited Talk]
* Masanori Imai (STARC) |
Growing complexity of SoC’s and reducing life cycle time of electronic products both are demanding higher design product... [more] | VLD2004-103 CPSY2004-69 pp.35-38 |
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