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All Technical Committee Conferences (Searched in: All Years)
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| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| SDM |
2007-03-15
13:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories
Yuichi Matsui, Kenzo Kurotsuchi, Osamu Tonomura, Takahiro Morikawa, Masaharu Kinoshita, Yoshihisa Fujisaki, Nozomu Matsuzaki, Satoru Hanzawa, Motoyasu Terao, Norikatsu Takaura, Hiroshi Moriya, Tomio Iwasaki (Hitachi), Masahiro Moniwa, Tsuyoshi Koga (Renesas) |
A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., c... [more] |
SDM2006-254
pp.1-6 |
| ICD, ITE-CE |
2006-12-15
12:05 |
Hiroshima |
|
Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding
Masakatsu Ishizaki, Takeshi Kumaki, Yutaka Kono, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology Corp.) |
[more] |
ICD2006-165
pp.125-130 |
| MW |
2006-11-22
11:35 |
Fukuoka |
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5GHz-Band CMOS double stacked cascode variable gain driver amplifier by switching common-source FET
Hiroomi Ueda, Kazutomi Mori, Mitsuhiro Shimozawa (Mitsubishi Electric Corp.), Tomoumi Yagasaki, Koichi Yahagi (Renesas Technology Corp.), Noriharu Suematsu (Mitsubishi Electric Corp.) |
[more] |
MW2006-143
pp.63-66 |
| ICD, SDM |
2006-08-18
12:05 |
Hokkaido |
Hokkaido University |
A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] |
SDM2006-148 ICD2006-102
pp.133-136 |
| ICD, SDM |
2006-08-18
14:35 |
Hokkaido |
Hokkaido University |
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits
Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] |
SDM2006-151 ICD2006-105
pp.149-153 |
| ICD |
2006-04-14
14:45 |
Oita |
Oita University |
An Internal Voltage Generation System of Flash Memory Module
Jiro Ishikawa, Toshihiro Tanaka, Akira Kato, Takashi Yamaki, Yukiko Umemoto, Takeshi Shimozato, Isao Nakamura, Yutaka Shinagawa (Renesas Technology Corp.) |
We present a new internal voltage generation system of flash memory module embedded in a microcontroller. One of the fea... [more] |
ICD2006-20
pp.109-113 |
| ICD, VLD |
2006-03-10
15:35 |
Okinawa |
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An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design
Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltag... [more] |
VLD2005-132 ICD2005-249
pp.61-66 |
| CAS, SIP, CS |
2006-03-06
15:30 |
Okinawa |
Univ of Ryukyu |
Buffer capacity evaluation of the bus using a memory bus SystemC model
Kozo Ishida, Midori Ono, Osamu Toyama (Mitsubishi Electric Corp.), Tetsuya Kagemoto, MasayukiKoyama (Renesas Technology Corp.), Shiro Hosotani (Mitsubishi Electric Corp.) |
[more] |
CAS2005-116 SIP2005-162 CS2005-109
pp.117-121 |
| ICD, ITE-CE |
2006-01-27
11:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Wide Band 3D Y/C Separation Circuit for PAL System with Reduced Memory Size
Toshihiro Gai, Masaki Yamakawa (Mitsubishi Electric), Sohichiroh Higashi (Mitsubishi Electric Micro-computer Application Software), Tsuyoshi Inoue (Renesas Technology) |
This paper reports how a 3D Y/C separation circuit of PAL system with a 27 MHz-fixed clock has been achieved using a sma... [more] |
ICD2005-217
pp.13-15 |
| SIP, ICD, IE, IPSJ-SLDM |
2005-10-20
16:30 |
Miyagi |
Ichinobo, Sakunami-Spa |
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Takayuki Gyohten, Fukashi Morishita, Hideyuki Noda (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) |
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated o... [more] |
SIP2005-113 ICD2005-132 IE2005-77
pp.107-112 |
| EMCJ |
2005-09-09
09:30 |
Kyoto |
Kyoto University |
Evaluation of Electric Field Caused by High Frequency Band Power Line Communication
Hitoshi Kubota (Mitsubishi Electric Corp.), Kenji Ogaki (Renesas Technology Corp.) |
Possibility of the extension of the usable frequency band for power line communication is under in dispute. This paper r... [more] |
EMCJ2005-66
pp.43-47 |
| EMCJ |
2004-12-10
16:15 |
Aichi |
Nagoya Institute of Technology |
A Study on Measurement of LSI Immunity for PCB Analysis
Kouji Ichikawa, Yukihiko Sakurai, Masashi Inagaki, Takeshi Matsui (DENSO), Yuichi Mabuchi (Hitachi), Atsushi Nakamura, Toru Hayashi (Renesas Technology) |
We have been developing an LSI model for EMS simulation in automotive electronic control units.
PCB immunity was analyz... [more] |
EMCJ2004-115
pp.77-82 |
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