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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2017-10-26 13:30 |
Miyagi | Niche, Tohoku Univ. | Pinning Voltage Control of CMOS Image Sensor by measuring sheet resistance at micro test structure in scribe line Yotaro Goto (RSMC), Tadasihi Yamaguchi, Masazumi Matsuura (REL), Koji Iizuka (RSMC)  SDM2017-59 |
[more] | SDM2017-59 pp.51-55 |
| HWS (2nd) |
2017-09-15 15:50 |
Tokyo | The introduction of authentication method using radio communication Yohei Kaieda, Hiroki Kunii (SECOM), Toshiya Uozumi, Masaya Miwa (Renesas Electronics) |
[more] | ||
| SDM, ICD, ITE-IST [detail] | 2017-07-31 10:40 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | A 65 nm 1.0V 1.84ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT Makoto Yabuuchi, Koji Nii, Shinji Tanaka (Renesas), Shinozaki Yoshihiro (Nippon Systemware), Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Shiro Kamohara (Renesas) SDM2017-33 ICD2017-21 |
[more] | SDM2017-33 ICD2017-21 pp.13-16 |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 13:00 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | [Invited Lecture]
A 3.2ppm/℃ Second-Order Temperature Compensated CMOS On-Chip Oscillator Using Voltage Ratio Adjusting Technique Guoqiang Zhang, Kosuke Yayama, Akio Katsushima, Takahiro Miki (Renesas Electronics) SDM2017-39 ICD2017-27 |
A CMOS on-chip oscillator (OCO) for local interconnection network (LIN) bus is presented. The temperature dependence of ... [more] | SDM2017-39 ICD2017-27 p.69 |
| SITE, EMM, ISEC, ICSS, IPSJ-CSEC, IPSJ-SPT [detail] | 2017-07-15 13:50 |
Tokyo | Security Evaluation of the Software Architecture of TEE-enabled Device and Its Open-source Implementation Naoki Yoshida (YNU), Kazuhiko Fukushima, Shigenori Miyauchi (Renesas Electronics), Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) ISEC2017-36 SITE2017-28 ICSS2017-35 EMM2017-39 |
It emerges that the use of security systems which separate device resources into Trusted Execution Environment (TEE) and... [more] | ISEC2017-36 SITE2017-28 ICSS2017-35 EMM2017-39 pp.267-274 |
|
| ICD | 2017-04-20 14:55 |
Tokyo | [Invited Lecture]
First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) ICD2017-7 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | ICD2017-7 pp.35-38 |
|
| ICD | 2017-04-20 15:20 |
Tokyo | [Invited Talk]
Embedded Flash Technology for Automotive Applications Masaya Nakano, Takashi Ito, Tadaaki Yamauchi, Yasuo Yamaguchi, Takashi Kono, Hideto Hidaka (Renesas Electronics) ICD2017-8 |
Higher fuel-efficient engine and advanced driver assistance system (ADAS) require the further progress of embedded Flash... [more] | ICD2017-8 pp.39-44 |
|
| ICD | 2017-04-21 10:25 |
Tokyo | [Invited Lecture]
A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL) ICD2017-12 |
[more] | ICD2017-12 pp.63-65 |
|
| DC | 2017-02-21 12:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77 |
Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which ke... [more] |
DC2016-77 pp.17-22 |
| SDM | 2017-01-30 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
First Demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and Beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) SDM2016-134 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | SDM2016-134 pp.17-20 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:25 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 |
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] | EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 pp.87-92 |
| SDM | 2016-11-10 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
SISPAD 2016 Review (1) Kenichiro Sonoda (Renesas Electronics) SDM2016-79 |
[more] | SDM2016-79 pp.1-7 |
| SDM | 2016-10-26 15:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2016-71 pp.15-20 |
| SDM | 2016-10-26 16:10 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias Yoshiki Yamamoto, Hideki Makiyama, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Shinkawata Hiroki, Shiro Kamohara, Yasuo Yamaguchi (Renesas), Nobuyuki Sugii (Hitachi), Tomoko Mizutani, Toshiro Hiramoro (UT) SDM2016-72 |
We demonstrated record 0.37V minimum operation voltage (VMIN) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks... [more] | SDM2016-72 pp.21-25 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 13:20 |
Osaka | Central Electric Club | [Invited Talk]
A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) SDM2016-64 ICD2016-32 |
This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heter... [more] | SDM2016-64 ICD2016-32 pp.105-110 |
| ICD | 2016-04-14 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics) ICD2016-1 |
An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micr... [more] | ICD2016-1 pp.1-6 |
| ICD | 2016-04-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2016-3 |
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology... [more] | ICD2016-3 pp.13-16 |
| ICD | 2016-04-15 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C Satoru Nakanishi, Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Kurafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi (Renesas) ICD2016-15 |
A first-ever 90nm embedded 1T-MONOS Flash macro is presented to realize automotive reliability and simple process integr... [more] | ICD2016-15 pp.77-81 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 15:45 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | A consideration on variation correction for fail prediction in LSI test Ryo Ogawa (NAIST), Yoshiyuki Nakamura (Renesas Semiconductor Package & Test Solutions), Michiko Inoue (NAIST) CPSY2015-158 DC2015-112 |
Recently, a test cost reduction using data mining has been attracted. It is expected to reduce the cost by predicting fa... [more] | CPSY2015-158 DC2015-112 pp.271-276 |
| SDM | 2016-01-28 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125 |
[more] | SDM2015-125 pp.21-25 |
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