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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-ARC, IPSJ-HPC 2023-12-06
10:30		 Okinawa Okinawa Industry Support Center
(Primary: On-site, Secondary: Online)		 Development of Genetic Algorithm for Grid Graph in Order/Degree Problem
Kimura Hiroto, Yoshiko Hanada (Kansai Univ.), Masahiro Nakao, Keiji Yamamoto (R-CCS) CPSY2023-32		 We propose a genetic algorithm for solving grid graph that is a kind of Order/Degree problems (ODP). Grid graph is an op... [more] CPSY2023-32
pp.31-35
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
11:45		 Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)		 Evaluation of reduced routing resources for HPC-Oriented CGRAs
Carlos Cortes, Boma Adhi, Tomohiro Ueno (RIKEN Center for Computational Science (R-CCS)), Yiyu Tan (Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima (Information Science and Technology The Univ. of Tokyo), Artur Podobas (KTH Royal Inst. of Technology), Kentaro Sato (RIKEN Center for Computational Science (R-CCS)) VLD2022-59 RECONF2022-82		  [more] VLD2022-59 RECONF2022-82
pp.19-23
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
16:20		 Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)		 Interface development for Python use of FPGA cluster ESSPER
Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT) VLD2022-62 RECONF2022-85		  [more] VLD2022-62 RECONF2022-85
pp.27-28
RECONF 2022-06-07
16:45		 Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)		 Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER
Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) RECONF2022-11		 This study evaluates the communication speed between FPGAs assuming the FPGA cluster ESSPER is a scalable and
flexible ... [more]		 RECONF2022-11
pp.48-49
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-24
16:45		 Online Online A study of an accelerator for CNN inference on FPGA clusters
Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS) VLD2021-60 CPSY2021-29 RECONF2021-68		 In this study, we propose a CNN accelerator for FPGA clusters, which accelerates the CNN inference process by distributi... [more] VLD2021-60 CPSY2021-29 RECONF2021-68
pp.61-66
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] 2022-01-25
14:05		 Online Online Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC
Boma Adhi, Carlos Cortes, Yiyu Tan (R-CCS), Takuya Kojima (Tokyo Univ.), Artur Podobas (KTH), Kentaro Sano (R-CCS) VLD2021-71 CPSY2021-40 RECONF2021-79		  [more] VLD2021-71 CPSY2021-40 RECONF2021-79
pp.126-131
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] 2021-01-25
09:50		 Online Online Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method
Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST) VLD2020-41 CPSY2020-24 RECONF2020-60		 (To be available after the conference date) [more] VLD2020-41 CPSY2020-24 RECONF2020-60
pp.13-18
RECONF 2020-09-10
13:55		 Online Online RECONF2020-20 (To be available after the conference date) [more] RECONF2020-20
pp.7-12
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-31
15:55		 Kanagawa Raiosha, Hiyoshi Campus, Keio University An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card
Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN) VLD2018-92 CPSY2018-102 RECONF2018-66		 We are developing and researching a common platform for high performance stream computing with Field Programmable Gate A... [more] VLD2018-92 CPSY2018-102 RECONF2018-66
pp.125-130
 Results 1 - 9 of 9  /   
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