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Committee Date Time Place Paper Title / Authors Abstract Paper #
NC, IBISML, IPSJ-MPS, IPSJ-BIO [detail] 2019-06-17
16:45		 Okinawa Okinawa Institute of Science and Technology Embedded AI implementation
Tadaaki Shiraishi (MMS), Koji Kinoshita (Ehime Univ) NC2019-10		 In order to realize CNN on edge terminals and realize inference processing such as image recognition, it is important to... [more] NC2019-10
pp.35-40
VLD 2015-03-03
11:35		 Okinawa Okinawa Seinen Kaikan A Virtual/Real Combined Verification Method for FPGAs
Yoshimasa Ishino (MMS) VLD2014-167		 The biggest advantage of FPGA is that can change the circuits at any time. Therefore, verification in virtual stage beco... [more] VLD2014-167
pp.85-89
DC, CPSY 2009-04-21
11:25		 Tokyo Akihabara Satellite Campus, Tokyo Metropolitan Univ. A Development Process with A Model Checking Criterion
Michitaka Inui (Mitsubishi Electric Micro-Computer Application Software Corp.), Nobukazu Yoshioka (NII) CPSY2009-2 DC2009-2		 We have proposed a process for solving problems that we have to apply the model checking in a company. Also we have prop... [more] CPSY2009-2 DC2009-2
pp.7-12
ICD, ITE-CE 2006-01-27
11:15		 Tokyo Kikai-Shinko-Kaikan Bldg. Wide Band 3D Y/C Separation Circuit for PAL System with Reduced Memory Size
Toshihiro Gai, Masaki Yamakawa (Mitsubishi Electric), Sohichiroh Higashi (Mitsubishi Electric Micro-computer Application Software), Tsuyoshi Inoue (Renesas Technology) 		This paper reports how a 3D Y/C separation circuit of PAL system with a 27 MHz-fixed clock has been achieved using a sma... [more] ICD2005-217
pp.13-15
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