IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS, ICD 2024-02-28
15:30		 Okinawa
(Primary: On-site, Secondary: Online)		 A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (JEDAT) VLD2023-102 HWS2023-62 ICD2023-91		  [more] VLD2023-102 HWS2023-62 ICD2023-91
pp.18-23
VLD, HWS, ICD 2024-02-28
15:55		 Okinawa
(Primary: On-site, Secondary: Online)		 Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat) VLD2023-103 HWS2023-63 ICD2023-92		 In this paper, for a three-layer bottleneck channel routing problem in which pins of each net are placed on the upper or... [more] VLD2023-103 HWS2023-63 ICD2023-92
pp.24-29
HWS, VLD 2023-03-03
09:55		 Okinawa
(Primary: On-site, Secondary: Online)		 Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72		 Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2022-101 HWS2022-72
pp.149-154
HWS, VLD 2023-03-03
10:20		 Okinawa
(Primary: On-site, Secondary: Online)		 Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT) VLD2022-102 HWS2022-73		 In analog integrated circuits, designs usually rely on the relative accuracy of device characteristics. The purpose of t... [more] VLD2022-102 HWS2022-73
pp.155-160
VLD, HWS [detail] 2022-03-07
09:35		 Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54		 Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
pp.7-12
SIP, CAS, VLD 2006-06-22
15:50		 Hokkaido Kitami Institute of Technology Sequence-Pair Based Compaction under Equi-Length Constraint
Takehiko Matsuo (Univ. of Kitakyushu), Keiji Kida (Jedat), Tetsuya Tashiro, Shigetoshi Nakatake (Univ. of Kitakyushu) 		Equi-length constraints are widely used for a sub-stitution for IR-drop or skew constrains. This paper provides a linear... [more] CAS2006-6 VLD2006-19 SIP2006-29
pp.29-34
 Results 1 - 6 of 6  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan