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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Daisuke Fukuda (Fujitsu Labs.)
Vice Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant Kazuki Ikeda (Hitachi)

Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Yasuhiro Takashima (Univ. of Kitakyushu)
Vice Chair Hiroki Sato (Sony LSI Design)
Secretary Takahide Sato (Yamanashi Univ.), Shinji Shimoda (Sony LSI Design)
Assistant Motoi Yamaguchi (TECHNOPRO), Yohei Nakamura (Hitachi)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Naoyuki Aikawa (TUS)
Vice Chair Kazunori Hayashi (Osaka City Univ), Yukihiro Bandou (NTT)
Secretary Masayoshi Nakamoto (Hiroshima Univ.), Katsumi Konishi (Hosei Univ.)
Assistant Kenjiro Sugimoto (Waseda Univ.)

Technical Committee on Mathematical Systems Science and its applications (MSS) [schedule] [select]
Chair Shigemasa Takai (Osaka Univ.)
Vice Chair Atsuo Ozaki (Osaka Inst. of Tech.)
Secretary Takahumi Kanazawa (Setsunan Univ.), Koichi Kobayashi (Hokkaido Univ.)
Assistant Naoki Hayashi (Osaka Univ.)

Conference Date Thu, Jun 18, 2020 09:55 - 16:30
Conference Place Online 
Address Please register from the following site.
Transportation Guide Please register from the following site.
Sponsors This conference is co-sponsored by IEEE Signal Processing Society Tokyo Joint Chapter. This conference is technical co-sponsored by IEEE Circuits and Systems Society Japan Chapter(IEEE CASS JC).This conference is technical co-sponsored by IEEE CEDA All Japan Joint Chapter.
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on MSS, CAS, SIP, VLD.

Thu, Jun 18 PM 
09:55 - 10:00
Thu, Jun 18 AM 
10:00 - 12:05
(1) 10:00-10:25 The Construction of Logical Layer in the 3rd Digital Linguistic Evolution (Electronic Information)
-- To become Homo Sapiens --
CAS2020-1 VLD2020-1 SIP2020-17 MSS2020-1
Kumon Tokumaru (Writer)
(2) 10:25-10:50 On numerical approximated solutions of an ordinary differential\ equation using a LSTM neural network CAS2020-2 VLD2020-2 SIP2020-18 MSS2020-2 Kazuya Ozawa, Kaito Isogai, Hideaki Okazaki (SIT)
(3) 10:50-11:15 A Study on AM-AM/PM Characteristics of RF Power Amplifiers CAS2020-3 VLD2020-3 SIP2020-19 MSS2020-3 Satoshi Tanaka (Murata Manufacturing)
(4) 11:15-11:40 Application of Analytic Method of Lossless Telegrapher's Equation to Quantum Mechanics CAS2020-4 VLD2020-4 SIP2020-20 MSS2020-4 Nobuo Nagai (Hokkaido Univ.), Hirofumi Sanada (HUS)
(5) 11:40-12:05 Role of Circuit Theory for Wave Phenomena in Physics CAS2020-5 VLD2020-5 SIP2020-21 MSS2020-5 Nobuo Nagai (Hokkaido Univ.), Hirofumi Sanada (HUS)
  12:05-13:10 Lunch Break ( 65 min. )
Thu, Jun 18 PM 
13:10 - 14:50
(6) 13:10-13:35 Simultaneous Design of Controllers and Decentralized Event-Triggering Conditions for Cyber-Physical Systems CAS2020-6 VLD2020-6 SIP2020-22 MSS2020-6 Koichi Kobayashi, Kyohei Nakaima, Yuh Yamashita (Hokkaido Univ.)
(7) 13:35-14:00 Characteristic Analyses and Generation of Maximally Asymmetric Functions CAS2020-7 VLD2020-7 SIP2020-23 MSS2020-7 Hiroshi Kanehagi, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(8) 14:00-14:25 Optimal Design for Level-Shifter-Less Approach using Channel Length Modulation & Body Biasing CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 Tatsuya Watanabe, Usami Kimiyoshi (SIT)
(9) 14:25-14:50 Thermal transient analysis of the heat generation and design of temperature control circuit in three-dimensional stacked chip CAS2020-9 VLD2020-9 SIP2020-25 MSS2020-9 Tomoaki Oikawa, Kimiyoshi Usami (Shibaura Inst. of Tech.)
  14:50-15:00 Break ( 10 min. )
Thu, Jun 18 PM 
15:00 - 16:30
(10) 15:00-16:30 [Panel Discussion]
The role of System and Signal Processing Subsociety
-- Pros & Cons of Online Video Meeting --
CAS2020-10 VLD2020-10 SIP2020-26 MSS2020-10
Shogo Muramatsu (Niigata Univ.), Shigemasa Takai (Osaka Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Kasunori Hayashi (Kyoto Univ.), Daisuke Fukuda (Fujitsu Lab.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yuichi Sakurai (Hitachi)
E-: iixj 
Announcement See also VLD's homepage:
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address Yohei Nakamura (Hitachi, Ltd.)
TEL: 080-1072-8751
E-: isj 
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address Masayoshi Nakamoto(Hiroshima University)
E: msy-u 
MSS Technical Committee on Mathematical Systems Science and its applications (MSS)   [Latest Schedule]
Contact Address Takafumi Kanazawa (Osaka University)
Tel: +81-6-6850-6388
E-: es-u 

Last modified: 2020-11-06 13:43:35

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