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*** All sessions was held as online conference. ***





Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Daisuke Fukuda (Fujitsu Labs.)
Vice Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Hidetsugu Irie (Univ. of Tokyo)
Vice Chair Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.)
Secretary Shinya Takameda (Hokkaido Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Assistant Shugo Ogawa (Hitachi), Eiji Arima (Univ. of Tokyo)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)
Assistant Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Hiroshi Inoue (Kyushu Univ.)
Secretary Satoshi Imamura (Fujitsu lab.), Ryota Shioya (Nagoya Univ.), Teruo Tanimoto (Kyushu Univ.), Koyo Nitta (NTT)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yuichi Nakamura (NEC)
Secretary Kenshu Seto (Tokyo City Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Kazuki Oya (Mitsubishi Electric), Masayuki Hiromoto (Fujistu Lab.)

Conference Date Mon, Jan 25, 2021 09:00 - 18:00
Tue, Jan 26, 2021 09:00 - 17:25
Topics FPGA Applications, etc. 
Conference Place  
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CPSY, RECONF, VLD.

Mon, Jan 25 AM  HPC
09:00 - 10:40
(1)
CPSY
09:00-09:25 VLD2020-39 CPSY2020-22 RECONF2020-58
(2)
RECONF
09:25-09:50 VLD2020-40 CPSY2020-23 RECONF2020-59
(3)
RECONF
09:50-10:15 Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method VLD2020-41 CPSY2020-24 RECONF2020-60 Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST)
(4)
RECONF
10:15-10:40 An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing VLD2020-42 CPSY2020-25 RECONF2020-61 Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN)
  10:40-10:55 Break ( 15 min. )
Mon, Jan 25 PM 
10:55 - 11:55
(5)
CPSY
10:55-11:55 [Invited Talk]
System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku" VLD2020-43 CPSY2020-26 RECONF2020-62
Yuichiro Ajima (Fujitsu)
  11:55-12:55 Break ( 60 min. )
Mon, Jan 25 PM 
12:55 - 14:10
(6)
CPSY
12:55-13:20 VLD2020-44 CPSY2020-27 RECONF2020-63
(7)
CPSY
13:20-13:45 VLD2020-45 CPSY2020-28 RECONF2020-64
(8)
CPSY
13:45-14:10 Throughput improvement of Responsive Link with High Speed Transceiver in FPGA VLD2020-46 CPSY2020-29 RECONF2020-65 Masahiko Takahashi, Yamasaki Nobuyuki (Keio Univ.)
  14:10-14:25 Break ( 15 min. )
Mon, Jan 25 PM 
14:25 - 16:05
(9)
CPSY
14:25-14:50 Evaluations of FPGA-based Neural Networks using of ODE VLD2020-47 CPSY2020-30 RECONF2020-66 Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
(10)
RECONF
14:50-15:15 Efficient Attention Mechanism by Softmax Function with Trained Coefficient VLD2020-48 CPSY2020-31 RECONF2020-67 Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT)
(11)
RECONF
15:15-15:40 A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA VLD2020-49 CPSY2020-32 RECONF2020-68 Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech)
(12)
RECONF
15:40-16:05 Implementation of Quantized Deep Neural Network on FPGA VLD2020-50 CPSY2020-33 RECONF2020-69 Pan Hongyi (AIST/The Univ. of Tokyo), Ben Ahmed Akram, Ikegami Tsutomu (AIST), Tominaga Kazuki (The Univ. of Tokyo), Kudoh Tomohiro (AIST/The Univ. of Tokyo)
  16:05-16:20 Break ( 15 min. )
Mon, Jan 25 PM 
16:20 - 18:00
(13)
VLD
16:20-16:45 Residual signed-digit number - residual binary number conversion algorithm VLD2020-51 CPSY2020-34 RECONF2020-70 Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(14)
VLD
16:45-17:10 Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA VLD2020-52 CPSY2020-35 RECONF2020-71 Wataru Okumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ)
(15)
VLD
17:10-17:35 Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval VLD2020-53 CPSY2020-36 RECONF2020-72 Yuki Okabe, Daisuke Kanemoto (Osaka Univ.), Tomoya Mochizuki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.)
(16)
VLD
17:35-18:00 High speed architectures of decimal counters VLD2020-54 CPSY2020-37 RECONF2020-73 Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
  18:00-18:30 Break ( 30 min. )
  18:30-20:30 Social Event ( 120 min. )
Tue, Jan 26 AM 
09:00 - 10:15
(17)
CPSY
09:00-09:25 Acceleration of Database Query Processing Using FPGA VLD2020-55 CPSY2020-38 RECONF2020-74 Hirohiko Ozaku (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
(18)
RECONF
09:25-09:50 FPGA Accelerator Design for Real-Time Object Detection VLD2020-56 CPSY2020-39 RECONF2020-75 Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba)
(19)
RECONF
09:50-10:15 FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot VLD2020-57 CPSY2020-40 RECONF2020-76 Yuichiro Niwa (ATLA), Taiki Fujii (eSOL)
  10:15-10:30 Break ( 15 min. )
Tue, Jan 26 PM 
10:30 - 11:45
(20)
CPSY
10:30-10:55 VLD2020-58 CPSY2020-41 RECONF2020-77
(21)
CPSY
10:55-11:20 Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching VLD2020-59 CPSY2020-42 RECONF2020-78 Shunta Kikuchi (AIST/The Univ. of Tokyo), Tsutomu Ikegami, Akram ben Ahmed (AIST), Tomohiro Kudoh (The Univ. of Tokyo/AIST), Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku (Univ. of Tsukuba)
(22)
RECONF
11:20-11:45 VLD2020-60 CPSY2020-43 RECONF2020-79 Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)
  11:45-12:45 Break ( 60 min. )
Tue, Jan 26 PM 
12:45 - 14:00
(23)
RECONF
12:45-13:10 SLM based FPGA-IP soft core VLD2020-61 CPSY2020-44 RECONF2020-80 Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
(24)
RECONF
13:10-13:35 Automated architecture exploration on Scala-based hardware development environment VLD2020-62 CPSY2020-45 RECONF2020-81 Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT)
(25) 13:35-14:00  
  14:00-14:15 Break ( 15 min. )
Tue, Jan 26 PM 
14:15 - 15:55
(26)
VLD
14:15-14:40 A new method for evaluating corruption metric and resilience of logic locking VLD2020-63 CPSY2020-46 RECONF2020-82 Shusaku Minami, Yusuke Matsunaga (Kyushu Univ.)
(27)
VLD
14:40-15:05 Mutation-Based Fuzzing Using Data Structure Captured via Data Generator VLD2020-64 CPSY2020-47 RECONF2020-83 Noriyuki Namba, Nagisa Ishiura (Kwansei Gakuin Univ.)
(28)
VLD
15:05-15:30 Detection of Vulnerability Inducing Code Optimization Based on Binary Code VLD2020-65 CPSY2020-48 RECONF2020-84 Yuka Azuma, Nagisa Ishiura (Kwansei Gakuin Univ.)
(29)
VLD
15:30-15:55 Performance Testing of VRP Optimization of C Compilers by Random Program Generation VLD2020-66 CPSY2020-49 RECONF2020-85 Daiki Murakami, Nagisa Ishiura (Kwansei Gakuin Univ.)
  15:55-16:10 Break ( 15 min. )
Tue, Jan 26 PM 
16:10 - 17:25
(30) 16:10-16:35  
(31) 16:35-17:00  
(32) 17:00-17:25  

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yuichi SAKURAI (Hitachi)
E-: iixj 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address CPSY WEB
https://www.ieice.org/~cpsy/ 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Yuichiro Shibata(Nagasaki Univ.)
E-: bacis-u 
Announcement http://www.ieice.org/~reconf/
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kenshu Seto (Tokyo City University)
E-: ktcu 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2020-12-22 13:41:56


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