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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Makoto Ikeda (Univ. of Tokyo)
Vice Chair Toshiyuki Shibuya (Fujitsu Labs.)
Secretary Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Takeshi Yamamura (Fujitsu Labs.)
Vice Chair Minoru Fujishima (Hiroshima Univ.)
Secretary Toshimasa Matsuoka (Osaka Univ.), Osamu Watanabe (Toshiba)
Assistant Shinichi Ouchi (AIST), Takeshi Yoshida (Hiroshima Univ.), Akira Tsuchiya (Kyoto Univ.), Pham Konkuha (Univ. of Electro-Comm.)

Technical Committee on Image Engineering (IE) [schedule] [select]
Chair Toshiaki Fujii (Nagoya Univ.)
Vice Chair Seishi Takamura (NTT), Takayuki Hamamoto (Tokyo Univ. of Science)
Secretary Akira Kubota (Chuo Univ.), Atsuro Ichigaya (NHK)
Assistant Hiroshi Sankoh (KDDI R&D Labs.), Shohei Matsuo (NTT)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Michiaki Muraoka (Kochi Univ.)
Secretary Naoki Iwata (Sony), Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.)

Conference Date Mon, Oct 7, 2013 10:30 - 16:55
Tue, Oct 8, 2013 09:00 - 12:15
Conference Place  
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Mon, Oct 7 AM  VLD(1)
Chair: Atsushi Kurokawa (Hirosaki Univ.)
10:30 - 11:45
10:30-10:55 A Memory Based Filed Programmable Device for Energy saving MCUs VLD2013-46 ICD2013-70 IE2013-46 Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.)
10:55-11:20 Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits VLD2013-47 ICD2013-71 IE2013-47 Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
11:20-11:45 Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit VLD2013-48 ICD2013-72 IE2013-48 Atsushi Ito, Makoto Ikeda (Univ. of Tokyo)
  11:45-13:00 Lunch ( 75 min. )
Mon, Oct 7 PM 
Chair: Michiaki Muraoka (Kochi Univ.)
13:00 - 14:00
13:00-14:00 [Invited Talk]
Technology Trends and Researches in Video Codec LSI VLD2013-49 ICD2013-73 IE2013-49
Satoshi Goto (Waseda Univ.)
  14:00-14:20 Break ( 20 min. )
Mon, Oct 7 PM 
Chair: Makoto Ikeda (Univ. of Tokyo)
14:20 - 15:20
14:20-15:20 [Invited Talk]
Standardization of HEVC/H.265 and a Real-time Encoder VLD2013-50 ICD2013-74 IE2013-50
Hiroharu Sakate, Nobuaki Motoyama (Mitsubishi Electric)
  15:20-15:40 Break ( 20 min. )
Mon, Oct 7 PM  IE/ICD(1)
Chair: Atsuro Ichigaya (NHK)
15:40 - 16:55
15:40-16:05 High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV) VLD2013-51 ICD2013-75 IE2013-51 Kentaro Seki, Tadayoshi Enomoto (Chuo Univ.)
16:05-16:30 A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition VLD2013-52 ICD2013-76 IE2013-52 Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ)
16:30-16:55 Set Operating Processor (SOP)
-- Application for Image recognition --
VLD2013-53 ICD2013-77 IE2013-53
Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC)
Tue, Oct 8 AM  VLD(2)
Chair: Makoto Sugihara (Kyushu Univ.)
09:00 - 10:15
09:00-09:25 A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations VLD2013-54 ICD2013-78 IE2013-54 Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
09:25-09:50 Scan-based attack on the LED block cipher using scan signatures VLD2013-55 ICD2013-79 IE2013-55 Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
09:50-10:15 A Bi-Linear Interpolation Unit Using Selector Logics VLD2013-56 ICD2013-80 IE2013-56 Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
  10:15-10:35 Break ( 20 min. )
Tue, Oct 8 AM  ICD/VLD(1)
Chair: Takeshi Yamamura (Fujitsu Labs.)
10:35 - 12:15
10:35-11:00 New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic VLD2013-57 ICD2013-81 IE2013-57 Xu Bai, Michitaka Kameyama (Tohoku Univ.)
11:00-11:25 A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage VLD2013-58 ICD2013-82 IE2013-58 Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
11:25-11:50 A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements VLD2013-59 ICD2013-83 IE2013-59 Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)
11:50-12:15 A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects VLD2013-60 ICD2013-84 IE2013-60 Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Shigetoshi Nakatake (Univ. of Kitakyushu)
E-: k-u 
Announcement See also VLD's homepage:
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Osamu Watanabe (Toshiba Corp.)
IE Technical Committee on Image Engineering (IE)   [Latest Schedule]
Contact Address Atsuro Ichigaya (NHK)
E-: ie-n2013 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Makoto Sugihara (Kyushu Univ.)
E gislrckshu-u 
Announcement Please see the IPSJ-SLDM page below:

Last modified: 2013-10-08 10:37:05

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