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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nozomu Togawa (Waseda Univ.)
Vice Chair Daisuke Fukuda (Fujitsu Labs.)
Secretary Yukihide Kohira (Univ. of Aizu), Yuichi Sakurai (Hitachi)
Assistant Kazuki Ikeda (Hitachi)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Makoto Nagata (Kobe Univ.)
Vice Chair Masafumi Takahashi (Toshiba-memory)
Secretary Masanori Natsui (Tohoku Univ.), Masatoshi Tsuge (Socionext)
Assistant Tetsuya Hirose (Osaka Univ.), Koji Nii (Floadia), Takeshi Kuboki (Kyushu Univ.)

Technical Committee on Image Engineering (IE) [schedule] [select]
Chair Hideaki Kimata (NTT)
Vice Chair Kazuya Kodama (NII), Keita Takahashi (Nagoya Univ.)
Secretary Kazuya Hayase (NTT), Yasutaka Matsuo (NHK)
Assistant Kyohei Unno (KDDI Research), Norishige Fukushima (Nagoya Inst. of Tech.)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Hidetsugu Irie (Univ. of Tokyo)
Vice Chair Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.)
Secretary Tomoaki Tsumura (Nagoya Inst. of Tech.), Shinya Takameda (Hokkaido Univ.)
Assistant Eiji Arima (Univ. of Tokyo), Shugo Ogawa (Hitachi)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Vice Chair Hiroshi Takahashi (Ehime Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Hiroshi Inoue (Kyushu Univ.)
Secretary Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Labs.), Yohei Hasegawa (Toshiba Memory)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yutaka Tamiya (Fujitsu Lab.)
Secretary Akira Tsuchiya (Univ. Shiga Prefecture), Hiroe Iwasaki (NTT), Toru Sasaki (Mitsubishi Electric)

Special Interest Group on Embedded Systems (IPSJ-EMB) [schedule] [select]

Conference Date Wed, Nov 13, 2019 10:05 - 17:45
Thu, Nov 14, 2019 09:15 - 17:00
Fri, Nov 15, 2019 09:15 - 17:00
Topics Design Gaia 2019 -New Field of VLSI Design- 
Conference Place Ehime Prefecture Gender Equality Center 
Address 450, Yamagoemachi, Matsuyama, Ehime, 791-8014, Japan
Transportation Guide https://www.ehime-joseizaidan.com/
Contact
Person
Prof. Senling Wang
Sponsors This conference is supported by IEEE CEDA All Japan Joint Chapter and IEEE CAS Japan Joint Chapter.
Participation Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Participant fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the participant fee page. We request the participant fee to participants who will attend the workshop(s) on VLD, DC, CPSY, RECONF, ICD, IE.

Wed, Nov 13 AM 
10:05 - 11:45
(1)
VLD
10:05-10:30 Takuya Kojima, Hideharu Amano (Keio Univ.)
(2)
VLD
10:30-10:55 Gate Level Netlist Function Classification Method Based on R-GCN Yuichiro Fujishiro, Hiroki Oyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.), Hiroaki Yasuda, Hiroto Ito (MITSUBISHI ELECTRIC ENGINEERING)
(3)
VLD
10:55-11:20
(4)
VLD
11:20-11:45 A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo)
Wed, Nov 13 AM 
10:30 - 11:45
(5) 10:30-10:55  
(6) 10:55-11:20  
(7) 11:20-11:45  
  11:45-13:00 Lunch Break ( 75 min. )
Wed, Nov 13 PM 
13:00 - 14:00
(8) 13:00-14:00  
Wed, Nov 13 PM 
14:10 - 15:00
(9) 14:10-15:00  
Wed, Nov 13 PM 
15:00 - 15:50
(10)
VLD
15:00-15:25 On-Chip Leakage Monitor based Temperature Sensor Circuit for Ultra Low Voltage Daisuke Sato, Kimiyoshi Usami (SIT)
(11)
VLD
15:25-15:50 Design of Reference-free CMOS Temperature Sensor with Statistical MOSFET Selection Shogo Harada, Mahfuzul Islam, Takashi Hisakado, Osami Wada (Kyoto Univ.)
Wed, Nov 13 PM 
16:00 - 17:45
  -  
Thu, Nov 14 AM 
09:15 - 10:30
(12)
RECONF
09:15-09:40
(13)
RECONF
09:40-10:05 FPGA implementation of ISA-based sparse CNN using Wide-SIMD Akira Jinguji, Shimpei Sato, Hiroki Nakahara (Titech)
(14)
RECONF
10:05-10:30 DNN accelerator for AI edge computing Yasuhiro Nakahara, Juntaro Chikama, Motoki Amagasaki (Kumamoto Univ.), Zhao Qian (Kyutech), Masahiro Iida (Kumamoto Univ.)
Thu, Nov 14 AM 
09:15 - 10:30
(15)
VLD
09:15-09:40 NBTI Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement Takumi Hosaka (Saitama Univ.), Shinichi Nishizawa (Fukuoka Univ.), RYO Kishida (Tokyo Univ. of Science), Takashi Matsumoto (The Univ. of Tokyo), Kazutoshi Kobayashi (Kyoto Institute of Tech.)
(16)
VLD
09:40-10:05 Device characteristic measurement for realizing CMOS-compatible non-volatile memory using FiCC Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(17)
VLD
10:05-10:30 NA Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
Thu, Nov 14 AM 
09:15 - 10:30
(18) 09:15-09:40  
(19) 09:40-10:05  
(20) 10:05-10:30  
Thu, Nov 14 AM 
10:45 - 11:45
(21) 10:45-11:45
  11:45-13:00 Lunch Break ( 75 min. )
Thu, Nov 14 PM 
13:00 - 14:00
(22) 13:00-14:00 [Keynote Address]
Prospect for Knowledge Intensive Society leveraged by VLSI Design
Hiroshi Nakamura (UTokyo)
Thu, Nov 14 PM 
14:15 - 15:30
(23)
ICD
14:15-14:40 Neural Network-based Lifetime Prediction and Reliability Enhancement Techniques for 3D NAND Flash Memory Masaki Abe, Ken Takeuchi (Chuo Univ.)
(24)
ICD
14:40-15:05 Ferroelectric FET-based Parallel Product-Sum Operation Neuromorphic Circuits Koki Kamimura, Susumu Nohmi, Ken Takeuchi (Chuo Univ.)
(25)
ICD
15:05-15:30 Design of an MTJ-Based Multiply-Accumulate Operation Circuit for an Energy-Efficient Binarized Neural Networks Tomoki Chiba, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)
Thu, Nov 14 PM 
14:15 - 15:30
(26)
VLD
14:15-14:40 Solving Traveling Salesman Problem Using Grid Partitioning via Ising-Model based Solver Akira Dan, Takeshi Nishikawa, Takashi Sato (Kyoto Univ.)
(27)
VLD
14:40-15:05
(28)
VLD
15:05-15:30 High-radix CORDIC algorithm for arcsine and arccosine calculation. Hiroshi Matsuoka, Naofumi Takagi (Kyoto Univ.)
Thu, Nov 14 PM 
14:40 - 15:05
(29)
RECONF
14:40-15:05
Thu, Nov 14 PM 
15:45 - 17:00
(30)
CPSY
15:45-16:10 A Study of Action Recognition Method using Pose Data toward Distributed Processing over Edge and Cloud Chikako Takasaki (Ocha Univ.), Atsuko Takefusa (NII), Hidemoto Nakada (AIST), Masato Oguchi (Ocha Univ.)
(31) 16:10-16:35  
(32)
CPSY
16:35-17:00 Domain Knowledge-aware Machine Learning System with Rule-based Guiding Tomoaki Shikina, Daichi Teruya, Hironori Nakajo (TAT)
Thu, Nov 14 PM 
15:45 - 17:00
(33) 15:45-16:10  
(34) 16:10-16:35  
(35) 16:35-17:00  
Thu, Nov 14 PM 
15:20 - 17:00
(36)
DC
15:20-15:45 A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.)
(37)
DC
15:45-16:10 Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults Yuta Nakano, Satoshi Ohtake (Oita Univ.)
(38)
DC
16:10-16:35 Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas)
(39)
DC
16:35-17:00 Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.)
Fri, Nov 15 AM 
09:15 - 10:30
(40)
CPSY
09:15-09:40 A preliminary study on obfuscation measures for hardware obfuscation Shotaro Yamada, Shuichi Ichikawa (TUT)
(41) 09:40-10:05  
(42) 10:05-10:30  
Fri, Nov 15 AM 
09:15 - 10:30
(43) 09:15-09:40  
(44) 09:40-10:05  
(45) 10:05-10:30  
Fri, Nov 15 AM 
09:15 - 10:30
(46)
ICD
09:15-09:40 A Study on Dependence between Performance Metrics of PUFs and the Number of Response Bits using PUF Numerical Model Tatsuya Oyama, Masayoshi Shirahata, Mitsuru Shiozaki, Shunsuke Okura (Ritsumeikan Univ.), Yohei Hori (AIST), Takeshi Fujino (Ritsumeikan Univ.)
(47)
ICD
09:40-10:05 Modeling attacks against device authentication using CMOS image sensor PUF Hiroshi Yamada, Shunsuke Okura, Mitsuru Shiozaki, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
(48)
ICD
10:05-10:30 Evaluation of operating performance of ECDSA hardware module. Yuya Takahashi, Monta kazuki (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
Fri, Nov 15 AM 
10:45 - 11:45
(49) 10:45-11:45 [Keynote Address]
Co-optimization of hardware architecture and algorithm for energy-efficient CNN inference
Daisuke Miyashita (Kioxia)
  11:45-13:00 Lunch Break ( 75 min. )
Fri, Nov 15 PM 
13:00 - 14:00
(50) 13:00-14:00 [Keynote Address]
Technology Trends of Persistent Memory
Satoshi Imamura (FLL)
Fri, Nov 15 PM 
14:15 - 15:05
(51) 14:15-15:05  
Fri, Nov 15 PM 
14:15 - 15:05
(52)
VLD
14:15-15:05 [Invited Talk]
Optimization Problems in Quantum Circuit Design
Shigeru Yamashita (Ritsumeikan Univ.)
Fri, Nov 15 PM 
14:15 - 15:30
(53)
ICD
14:15-14:40 Triple-Layered Ring Oscillators and Image Sensors Developed by Direct Bonding of SOI Wafers Masahide Goto (NHK), Yuki Honda (NHK-ES), Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi (Univ. of Tokyo), Eiji Higurashi (AIST), Hiroshi Toshiyoshi, Toshiro Hiramoto (Univ. of Tokyo)
(54)
IE
14:40-15:05 Highly sensitive and HDR image sensor using CTIA pixel circuit Yotaro Imai, Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS)
(55)
IE
15:05-15:30 HDR Imaging with Considering Spatial Resolution Deterioration and Motion Blur using Multiple-Exposure-Time Image Sensor Masahito Shimamoto, Yusuke Kameda, Takayuki Hamamoto (TUS)
Fri, Nov 15 PM 
15:20 - 17:00
(56)
CPSY
15:20-15:45 Evaluation of Inter-chip Inductive Coupling Wireless Communication Technology Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano (Keio Univ.)
(57)
CPSY
15:45-16:10 Ryohei Tomura, Takuya Kojima, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Masaaki Kondo (UTokyo)
(58)
CPSY
16:10-16:35 Low Latency Interrupt Handling Scheme By Using Interrupt Wake-Up Mechanism Ryo Wada, Nobuyuki Yamasaki (Keio Univ.)
(59)
CPSY
16:35-17:00 Non-stop embedded OS with Trace Buffer Haruki Shishido, Yamasaki Nobuyuki (Keio Univ.)
Fri, Nov 15 PM 
15:20 - 17:00
(60)
VLD
15:20-15:45 A Method of Parallel Computing for Detailed Routing on Ample Areas Yuya Shijo, Kunihiro Fujiyoshi (TUAT)
(61)
VLD
15:45-16:10 Lithography Hotspot Detection Based on Feature Vectors Considering Wire Width and Distance Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(62)
VLD
16:10-16:35 Analysis of databases used for hot spot test cases Hiroki Ogura, Hidekazu Takahashi, Sinpei Sato, Atsushi Takahashi (Tokyo Tech)
(63)
VLD
16:35-17:00 Mask Optimization Considering Process Variation by Subgradient Method Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA)
Fri, Nov 15 PM 
15:45 - 17:00
(64)
ICD
15:45-16:10 Design of optimal NV-memory configuration for hybrid SSD with QLC NAND flash memory Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi (Chuo Univ.)
(65)
ICD
16:10-16:35 A 16 Gb/s Differential Transmitter With Far-End Crosstalk Cancellation Using Injection Timing Control Daigo Takahashi (The Univ. of Tokyo), Yusuke Fujita, Satoshi Miura (THine Electronics), Tetsuya Iizuka (The Univ. of Tokyo)
(66)
ICD
16:35-17:00 A Study on DCDC Converter for RF Energy Harvesting Applications Munkhzul Munkhtsog, Koichiro Ishibashi (UEC)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yukihide Kohira (Univ. of Aizu)
E-: u-ai 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Masanori Natsui (Tohoku University)
E-: iec 
IE Technical Committee on Image Engineering (IE)   [Latest Schedule]
Contact Address Kei Kawamura (KDDI Research)
E-: ie-n2017 
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Akira Asato (FUJITSU)
E-: a

Hidetsugu Irie (the University of Tokyo)
TEL +81-3-5841-6788
E-: iemtltu-

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/ 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E-: ain-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Masato Motomura(Hokkaido Univ.)
E-: isti 
Announcement http://www.ieice.org/~reconf/
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Akira Tsuchiya (The University of Shiga Prefecture)
E-: aeusp 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/
IPSJ-EMB Special Interest Group on Embedded Systems (IPSJ-EMB)   [Latest Schedule]
Contact Address  


Last modified: 2019-11-04 15:52:34


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