|
|
| Chair |
|
Kentaro Sano (RIKEN) |
| Vice Chair |
|
Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.) |
| Secretary |
|
Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.) |
| Assistant |
|
Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.) |
|
| Conference Date |
Tue, Jun 7, 2022 13:00 - 17:05
Wed, Jun 8, 2022 09:20 - 17:40 |
| Topics |
Reconfigurable system, etc. |
| Conference Place |
Center for Computational Sciences, Tsukuba Univ. and Zoom |
| Address |
1-1-1 Tennodai, Tsukuba, Ibaraki 305-8577 |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF. |
Tue, Jun 7 PM
13:00 - 14:15 |
| (1) |
13:00-13:25 |
Accelerating Deep Learning-based Path Planning Method on FPGAs  RECONF2022-1 |
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
| (2) |
13:25-13:50 |
RECONF2022-2 |
Shoin Maeda, Hiroshi Nakamura, Hideki Takase (UT) |
| (3) |
13:50-14:15 |
Hardware implementation of the protocol for ROS2 and robot modules without CPU RECONF2022-3 |
Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Tue, Jun 7 PM
14:25 - 16:05 |
| (4) |
14:25-14:50 |
Performance Evaluation of Fault-Tolerant Routing Methods Using NAS Parallel Benchmarks RECONF2022-4 |
Yota Kurokawa, Masaru Fukushi (Yamaguchi Univ.) |
| (5) |
14:50-15:15 |
Vector Register Sharing Mechanism for Hardware Acceleration RECONF2022-5 |
Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) |
| (6) |
15:15-15:40 |
Optically reconfigurable gate array VLSI with a perfect parallel configuration function RECONF2022-6 |
Sae Goto, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| (7) |
15:40-16:05 |
290 Mrad total-ionizing-dose tolerance experiment for an optically reconfigurable gate array VLSI RECONF2022-7 |
Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
| |
16:05-16:15 |
Break ( 10 min. ) |
Tue, Jun 7 PM
16:15 - 17:05 |
| (8) |
16:15-16:25 |
RECONF2022-8 |
|
| (9) |
16:25-16:35 |
An Implementation of a Pattern-matching Accelerator on a RISC-V Processor RECONF2022-9 |
Riku Takayama, Jubee Tada (Yamagata Univ.) |
| (10) |
16:35-16:45 |
Design of a Quantum Annealing Accelerator for Sparse Ising Model RECONF2022-10 |
Yuta Ohma, Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.) |
| (11) |
16:45-16:55 |
Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER RECONF2022-11 |
Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) |
| (12) |
16:55-17:05 |
Development of Vehicles GPS Time Synchronized Vibration Measurement System for Bridge Health Monitoring RECONF2022-12 |
Masaaki Ono, Ryota Shin, Yukihiko Okada, Ryosuke Yamamoto (Univ. of Tsukuba) |
| |
17:05-17:25 |
( 20 min. ) |
Wed, Jun 8 AM
09:20 - 10:35 |
| (13) |
09:20-09:45 |
Investigation of methods to accelerate inference processing by deep learning RECONF2022-13 |
Seiya Iwamoto, Chikako Nakanishi (OIT) |
| (14) |
09:45-10:10 |
Consideration of speeding up AI inference processing by cooperative operation of hardware and software RECONF2022-14 |
Tomoya Kawakami, Chikako Nakanishi (OIT) |
| (15) |
10:10-10:35 |
RECONF2022-15 |
|
| |
10:35-10:45 |
Break ( 10 min. ) |
Wed, Jun 8 AM
10:45 - 12:00 |
| (16) |
10:45-11:10 |
RECONF2022-16 |
|
| (17) |
11:10-11:35 |
RECONF2022-17 |
|
| (18) |
11:35-12:00 |
Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters RECONF2022-18 |
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ) |
| |
12:00-14:00 |
Break ( 120 min. ) |
Wed, Jun 8 PM
14:00 - 14:50 |
| (19) |
14:00-14:50 |
RECONF2022-19 |
|
| |
14:50-15:00 |
Break ( 10 min. ) |
Wed, Jun 8 PM
15:00 - 16:15 |
| (20) |
15:00-15:25 |
Regularization based CNN Optimizing and the acceleration on FPGA RECONF2022-20 |
Hengyi Li, Xuebin Yue, Lin Meng (RU) |
| (21) |
15:25-15:50 |
A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration RECONF2022-21 |
Li Qi, Li Hengyi, Meng Lin (Ritsumeikan Univ.) |
| (22) |
15:50-16:15 |
Structural Sparsification of Activations and Weights for Low Latency Implementation of CNN RECONF2022-22 |
Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) |
| |
16:15-16:25 |
Break ( 10 min. ) |
Wed, Jun 8 PM
16:25 - 17:40 |
| (23) |
16:25-16:50 |
A Parallel Processing of Point Feature Histogram on FPGAs RECONF2022-23 |
Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
| (24) |
16:50-17:15 |
RECONF2022-24 |
|
| (25) |
17:15-17:40 |
RECONF2022-25 |
|
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Last modified: 2022-06-08 14:23:19
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