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Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Mineo Kaneko
Vice Chair Tetsuro Itakura
Secretary Masahide Abe, Yuichi Nakamura
Assistant Takafumi Yamaji

Conference Date Mon, Jan 29, 2007 13:00 - 18:05
Tue, Jan 30, 2007 09:30 - 12:45
Topics  
Conference Place Ehime University 
Address Bunkyo-cho 3, Matsuyama, Ehime, 790-8577, Japan
Transportation Guide http://www.ehime-u.ac.jp/map/access.html
Contact
Person
Associate Professor Hiroshi Takahashi
(089)927-9000
Sponsors This conference is co-sponsored by the IEEE CAS Society Shikoku Chapter.

Mon, Jan 29 PM 
13:00 - 18:05
(1) 13:00-13:25 A design method of SAW filters based on a lumped-constant network model Tetsuo Nishi (Waseda Univ.), Tomokazu Komazaki (Komazaki Network Lab)
(2) 13:25-13:50 Topological Analysis of DC Component of Averaged Power in Switching DC-DC Converters Masato Ogata (Kyushu Sangyo Univ.), Tetsuo Nishi (Waseda Univ.)
(3) 13:50-14:15 Noise analyses of single to poly-phase conversion with a frequency converter Takafumi Yamaji, Tetsuro Itakura (Toshbia), Hiroshi Tanimoto (Kitami Institute of Technology)
  14:15-14:35 Break ( 20 min. )
(4) 14:35-15:00 Study on a TOPS DPS Architecture Hiroshi Suzuki, Takao Nishitani, Hachiro Fujita (TMU)
(5) 15:00-15:25 Smearing-Desmearing, Wavelet Transform Digital Watermarking Based on Visual Masking Effect having tolerance in camera shoot Kentaro Okuhara, Toshiyuki Uto, Kenji Ohue (Ehime Univ.)
(6) 15:25-15:50 An improved LMS algorithm based on interleaving and smearing Katsutoshi Sonogi, Toshiyuki Uto, Kenji Ohue (Ehime Univ.)
  15:50-16:10 Break ( 20 min. )
(7) 16:10-17:00 [Invited Talk]
Web Systems for Conference/Organization Management
Satoshi Taoka (Hiroshima Univ.)
  17:00-17:15 Break ( 15 min. )
(8) 17:15-18:05 [Invited Talk]
Efficient Problem Solving for Combinatorial Optimization Using FPGAs
Shin'ichi Wakabayashi (Hiroshima City Univ.)
Tue, Jan 30 AM 
09:30 - 12:45
(9) 09:30-09:55 Experiment-based Evaluation of Algorithm Performance for the 2- or 3-Vertex Connectivity Augmentation Problem Hiroharu Sumiyoshi, Daisuke Takafuji, Satoshi Taoka, Toshimasa Watanabe (Hiroshima Univ.)
(10) 09:55-10:20 Improvement of track layout of bipartite graph subdivisions Miki Miyauchi (NTT)
(11) 10:20-10:45 A Circuit Partitioning Algorithm for Multi-FPGA Systems with Time-multiplexed I/Os Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
  10:45-11:05 Break ( 20 min. )
(12) 11:05-11:30 Remote hwObject hardware structure of hw/sw complex Hiroaki Iijima, Hiroshi Kishimoto, Masatoshi Sekine (tuat)
(13) 11:30-11:55 Multilevel control circuit of hwObject for servo control system Hiroaki Maekawa, Hiroaki Iijima, Masatoshi Sekine (TUAT)
(14) 11:55-12:20 Computational Complexity of Simultaneous Optimization of Skew, Schedule and Clock in High-Level Synthesis Takayuki Obata, Mineo Kaneko (JAIST)
(15) 12:20-12:45 A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake (NAIST), Mineo Kaneko (JAIST), Hideo Fujiwara (NAIST)

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CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
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Last modified: 2006-11-27 21:01:26


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