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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nozomu Togawa (Waseda Univ.)
Vice Chair Daisuke Fukuda (Fujitsu Labs.)
Secretary Yukihide Kohira (Univ. of Aizu), Yuichi Sakurai (Hitachi)
Assistant Kazuki Ikeda (Hitachi)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Hidetsugu Irie (Univ. of Tokyo)
Vice Chair Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.)
Secretary Tomoaki Tsumura (Nagoya Inst. of Tech.), Shinya Takameda (Hokkaido Univ.)
Assistant Eiji Arima (Univ. of Tokyo), Shugo Ogawa (Hitachi)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Hiroshi Inoue (Kyushu Univ.)
Secretary Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Labs.), Yohei Hasegawa (Toshiba Memory)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yutaka Tamiya (Fujitsu Lab.)
Secretary Akira Tsuchiya (Univ. Shiga Prefecture), Hiroe Iwasaki (NTT), Toru Sasaki (Mitsubishi Electric)

Conference Date Wed, Jan 22, 2020 11:00 - 18:10
Thu, Jan 23, 2020 09:30 - 20:30
Fri, Jan 24, 2020 09:30 - 17:05
Topics FPGA Applications, etc. 
Conference Place  
Transportation Guide https://www.keio.ac.jp/en/maps/hiyoshi.html
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Participation Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Participant fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the participant fee page. We request the participant fee to participants who will attend the workshop(s) on RECONF, VLD, CPSY.

Wed, Jan 22 AM 
11:00 - 12:15
(1)
RECONF
11:00-11:25 VLD2019-54 CPSY2019-52 RECONF2019-44 Honda Koki, Wei Kaijie (Keio Univ.), Arai Masatoshi (Saitama Univ.), Amano Hideharu (Keio Univ.)
(2)
RECONF
11:25-11:50 Task offloading from vector processor to FPGA through PCIe connection VLD2019-55 CPSY2019-53 RECONF2019-45 Kohei Hijikata (Tohoku Univ.), Tomohiro Ueno (RIKEN), Ryusuke Egawa, Hiroyuki Takizawa (Tohoku Univ.), Kentaro Sano (RIKEN)
(3)
RECONF
11:50-12:15 DDR4 SDRAM controller for real-time processing VLD2019-56 CPSY2019-54 RECONF2019-46 So Haramura, Nobuyuki Yamasaki (Keio Univ.)
  12:15-13:30 Lunch Break ( 75 min. )
Wed, Jan 22 PM 
13:30 - 15:10
(4)
CPSY
13:30-13:55 A Consideration of NAT Traversal Function for MPI Runtime Environment on Android OS VLD2019-57 CPSY2019-55 RECONF2019-47 Masahiro Nissato, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
(5)
CPSY
13:55-14:20 VLD2019-58 CPSY2019-56 RECONF2019-48
(6)
CPSY
14:20-14:45 Implementation and Evaluation of a Router on a Multi-FPGA System VLD2019-59 CPSY2019-57 RECONF2019-49 Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
(7)
CPSY
14:45-15:10 Performance Evaluation of Using Multi-Switch on a Multi-FPGA System VLD2019-60 CPSY2019-58 RECONF2019-50 Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
  15:10-15:25 Break ( 15 min. )
Wed, Jan 22 PM 
15:25 - 16:40
(8)
VLD
15:25-15:50 Increasing Test Variation for C Compilers by Equivalent Mutant Generation VLD2019-61 CPSY2019-59 RECONF2019-51 Hiroki Maeda, Nagisa ishiura (Kwansei Gakuin Univ.)
(9)
VLD
15:50-16:15 Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer VLD2019-62 CPSY2019-60 RECONF2019-52 Yoko Higuchi, Nagisa Ishiura, Namba Noriyuki (Kwansei Gakuin Univ.)
(10)
VLD
16:15-16:40 On logic locking method with affine transformation VLD2019-63 CPSY2019-61 RECONF2019-53 Yusuke Matsunaga (Kyushu Univ.)
  16:40-16:55 Break ( 15 min. )
Wed, Jan 22 PM 
16:55 - 18:10
(11)
RECONF
16:55-17:20 A Comparison of Filter for Convolutional Neural Network towards Hardware Implementation VLD2019-64 CPSY2019-62 RECONF2019-54 Kosuke Akimoto, Youki Sada, Shimpei Sato, Hiroki Hakahara (Tokyo Tech)
(12)
RECONF
17:20-17:45 Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks VLD2019-65 CPSY2019-63 RECONF2019-55 Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (Titech)
(13)
RECONF
17:45-18:10 An FPGA Implementation of Monocular Depth Estimation VLD2019-66 CPSY2019-64 RECONF2019-56 Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)
Thu, Jan 23 AM 
09:30 - 10:45
(14)
CPSY
09:30-09:55 An Efficient Cooperative Model Update using On-Device Learning VLD2019-67 CPSY2019-65 RECONF2019-57 Rei Ito, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
(15)
CPSY
09:55-10:20 A Light-Weight Reinforcement Learning using Online Sequential Learning VLD2019-68 CPSY2019-66 RECONF2019-58 Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
(16) 10:20-10:45  
  10:45-11:00 Break ( 15 min. )
Thu, Jan 23 AM 
11:00 - 12:15
(17)
VLD
11:00-11:25 Memory access optimization for convolution with scheduling transformations of dependence graphs VLD2019-69 CPSY2019-67 RECONF2019-59 Takayuki Todokoro, Kenshu Seto (TCU)
(18)
VLD
11:25-11:50 Full Hardware Synthesis of FreeRTOS-Based Systems VLD2019-70 CPSY2019-68 RECONF2019-60 Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
(19)
VLD
11:50-12:15 Binary Synthesis from RISC-V Executables VLD2019-71 CPSY2019-69 RECONF2019-61 Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.)
  12:15-13:30 Lunch Break ( 75 min. )
Thu, Jan 23 PM 
13:30 - 15:10
(20)
RECONF
13:30-13:55 Design and implementation of a RISC-V computer system running Linux in Verilog HDL VLD2019-72 CPSY2019-70 RECONF2019-62 Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech)
(21)
RECONF
13:55-14:20 Design and implementation of a RISC-V soft processor adopting five-stage pipelining VLD2019-73 CPSY2019-71 RECONF2019-63 Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech)
(22)
RECONF
14:20-14:45 VLD2019-74 CPSY2019-72 RECONF2019-64
(23)
RECONF
14:45-15:10 Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation VLD2019-75 CPSY2019-73 RECONF2019-65 Tomohiro Yoneda (NII)
  15:10-15:25 Break ( 15 min. )
Thu, Jan 23 PM 
15:25 - 16:40
(24)
CPSY
15:25-15:50 FPGA-based Stream Data Aggregation for Large Sliding-Windows VLD2019-76 CPSY2019-74 RECONF2019-66 Masaki Osaka (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
(25)
CPSY
15:50-16:15 VLD2019-77 CPSY2019-75 RECONF2019-67 ()
(26)
CPSY
16:15-16:40 Accelerating 2D LiDAR SLAM Algorithm using FPGA VLD2019-78 CPSY2019-76 RECONF2019-68 Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
  16:40-16:55 Break ( 15 min. )
Thu, Jan 23 PM 
16:55 - 20:30
(27)
CPSY
16:55-17:55 VLD2019-79 CPSY2019-77 RECONF2019-69
  17:55-18:30 Break ( 35 min. )
(28) 18:30-20:30  
Fri, Jan 24 AM 
09:30 - 10:45
(29)
RECONF
09:30-09:55 A Case Study of Development of Signal Processing Systems with RFSoC VLD2019-80 CPSY2019-78 RECONF2019-70 Ryohei Niwase (e-trees), Makoto Negoro, Yuta Kawai (Osaka Univ.), Takefumi Miyoshi (e-trees)
(30)
RECONF
09:55-10:20 Quantum control of electron spin qubit with RFSoC VLD2019-81 CPSY2019-79 RECONF2019-71 Yuta Kawai, Takato Koide, Hiroki Imawaka, Koichiro Miyanishi (Osaka Univ.), Ryohei Niwase, Takefumi Miyoshi (e-trees), Makoto Negoro, Akinori Kagawa (Osaka Univ.)
(31)
RECONF
10:20-10:45 Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect VLD2019-82 CPSY2019-80 RECONF2019-72 Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao (SIT)
  10:45-11:00 Break ( 15 min. )
Fri, Jan 24 AM 
11:00 - 12:15
(32)
CPSY
11:00-11:25 Parameter Aggregation using Software Switch for Multi-GPU Deep Learning VLD2019-83 CPSY2019-81 RECONF2019-73 Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani (Keio Univ.)
(33)
CPSY
11:25-11:50 Implementation of high speed rainbow table generation using Keccak hashing algorithm on CUDA VLD2019-84 CPSY2019-82 RECONF2019-74 Nguyen Dat Thuong, Keisuke Iwai, Takashi Matsubara, Takakazu Kurokawa (NDA)
(34)
CPSY
11:50-12:15 Prioritized Resource Management for Reservation Stations VLD2019-85 CPSY2019-83 RECONF2019-75 Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.)
  12:15-13:30 Lunch Break ( 75 min. )
Fri, Jan 24 PM 
13:30 - 15:10
(35)
VLD
13:30-13:55 An FPGA implementation of arc-sine high-radix CORDIC algorithm VLD2019-86 CPSY2019-84 RECONF2019-76 Hiroshi Matsuoka, Naofumi Takagi (Kyoto Univ.), Kazuyoshi Takagi (Mie Univ.)
(36)
VLD
13:55-14:20 Edge detection algorithms using stochastic architectures for various images VLD2019-87 CPSY2019-85 RECONF2019-77 Naoto Shinozaki, Kimiyoshi Usami (SIT)
(37)
VLD
14:20-14:45 An Approach to Approximate Multiplier Optimization VLD2019-88 CPSY2019-86 RECONF2019-78 Xinpei Zhang, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. Tokyo)
(38)
VLD
14:45-15:10 Partial synthesis method based on Column-wise verification for integer multipliers VLD2019-89 CPSY2019-87 RECONF2019-79 Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
  15:10-15:25 Break ( 15 min. )
Fri, Jan 24 PM 
15:25 - 17:05
(39)
RECONF
15:25-15:50 Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs VLD2019-90 CPSY2019-88 RECONF2019-80 Yuya Kawano, Yuto Tsukita, Jun Furuta, Kazutoshi Kobayashi (KIT)
(40)
RECONF
15:50-16:15 VLD2019-91 CPSY2019-89 RECONF2019-81
(41)
RECONF
16:15-16:40 VLD2019-92 CPSY2019-90 RECONF2019-82
(42)
RECONF
16:40-17:05 Study of stacked type logic LSI with fabrication technology of 3D flash memory. VLD2019-93 CPSY2019-91 RECONF2019-83 Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst of Tech.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yukihide Kohira (Univ. of Aizu)
E-: u-ai 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address CPSY WEB
https://www.ieice.org/~cpsy/ 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Masato Motomura(Hokkaido Univ.)
E-: isti 
Announcement http://www.ieice.org/~reconf/
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Akira Tsuchiya (The University of Shiga Prefecture)
E-: aeusp 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2020-01-14 19:39:10


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