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Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Hideto Hidaka (Renesas)
Vice Chair Makoto Nagata (Kobe Univ.)
Secretary Makoto Takamiya (Univ. of Tokyo), Takashi Hashimoto (Panasonic)
Assistant Masanori Natsui (Tohoku Univ.), Masatoshi Tsuge (Socionext), Hiroyuki Ito (Tokyo Inst. of Tech.), Pham Konkuha (Univ. of Electro-Comm.)

Conference Date Thu, Apr 19, 2018 10:10 - 17:25
Fri, Apr 20, 2018 09:55 - 15:45
Topics  
Conference Place  
Sponsors This conference is co-sponsored by IEEE SSCS Japan Chapter and IEEE SSCS Kansai Chapter.
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on ICD.

Thu, Apr 19 AM 
10:10 - 11:50
(1) 10:10-10:35 Reliability Enhancement Technique with Horizontal Error Detection and Vertical-LDPC in 3D-TLC NAND Flash Memories ICD2018-1 Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi (Chuo Univ.)
(2) 10:35-11:00 Application-optimized heterogeneously-integrated storage with non-volatile memories ICD2018-2 Chihiro Matsui, Ken Takeuchi (Chuo Univ.)
(3) 11:00-11:50 [Invited Talk]
Data-aware Computing with Highly Reliable SSD System ICD2018-3
Ken Takeuchi (Chuo Univ.)
  11:50-13:00 ( 70 min. )
Thu, Apr 19 PM 
13:00 - 14:40
(4) 13:00-13:50 [Invited Talk]
VLSI implementation of chaotic Boltzmann machine for deep learning hardware ICD2018-4
Takashi Morie, Masatoshi Yamaguchi, Ichiro Kawashima, Hakaru Tamukoh (Kyushu Inst. of Tech.)
(5) 13:50-14:40 [Invited Talk]
Hard- and Soft- Synchronized Developments of Resistive Analog Neuro Devices and Systems ICD2018-5
Hiroyuki Akinaga, Hisashi Shima, Yasuhisa Naitoh (AIST), Tetsuya Asai (Hokkaido Univ.)
  14:40-14:55 Break ( 15 min. )
Thu, Apr 19 PM 
14:55 - 17:25
(6) 14:55-15:45 [Invited Talk]
Low power Deep Learning hardware using emerging analog non-volatile memory
Irina Kataeva (DENSO Corp.)
(7) 15:45-16:35 [Invited Talk]
Introduction of the Latest GPU Technology for AI
-- How to deal with the DDR Memory Band Width Slow Improvement --
Toru Baji (NVIDIA)
(8) 16:35-17:25 [Invited Talk]
Problem solving of artificial intelligence with the Memorism processor ICD2018-6
Katsumi Inoue (AOT), Pham Cong-Kha (UEC)
Fri, Apr 20 AM 
09:55 - 11:50
(9) 09:55-10:20 [Invited Lecture]
A new core transistor equipped with NVM functionality without using any emerging memory materials ICD2018-7
Yasuhiro Taniguchi, Shoji Yoshida, Owada Fukuo, Yutaka Shinagawa, Hideo Kasai (Floadia), Lin Jia You, Wei I Huan (PTC), Daisuke Okada, Koichi Nagasawa, Kosuke Okuyama (Floadia)
(10) 10:20-10:45 [Invited Lecture]
An Implementation of 2RW Dual-Port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT ICD2018-8
Yohei Sawada, Yoshiki Yamamoto, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi (REL), Yoshihiro Shinozaki, Kyoji Ito (NSW), Shinji Tanaka, Nii Koji, Shiro Kamohara (REL)
(11) 10:45-11:10 [Invited Lecture]
A Dynamic Power Reduction in Synchronous 2RW 8T Dual-Port SRAM by Adjusting Wordline Pulse Timing with Same/Different Row Access Mode ICD2018-9
Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii (REL)
(12) 11:10-11:50 [Invited Talk]
A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology ICD2018-10
Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Toshifumi Hashimoto (TMC), Hao Nguyen, Ken Cheah, Hiroshi Sugawara, Seungpil Lee (WDC), Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura (TMC)
  11:50-13:00 ( 70 min. )
Fri, Apr 20 PM 
13:00 - 15:45
(13) 13:00-13:50 [Invited Talk]
Random Circuits for Information Security ICD2018-11
Hirofumi Shinohara (Waseda Univ.)
(14) 13:50-14:40 [Invited Talk]
Memory LSI using crystalline oxide semiconductor FET ICD2018-12
Jun Koyama, Takako Seki, Yuto Yakubo, Satoru Ohshita, Kazuma Furutani, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda (SEL), Masahiro Fujita (The Univ. of Tokyo), Shunpei Yamazaki (SEL)
  14:40-14:55 Break ( 15 min. )
(15) 14:55-15:45 [Invited Talk]
Design and Development of a memory-based reconfigurable logic device ICD2018-13
Mamoru Ohara (TIRI), Masayuki Sato (TRL), Tadashi Okabe (TIRI), Mitsunori Katsu (TRL)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.
Invited LectureEach speech will have 20 minutes for presentation and 5 minutes for discussion.
Invited TalkEach speech will have 40 minutes for presentation and 10 minutes for discussion.

Contact Address and Latest Schedule Information
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address  


Last modified: 2018-03-04 23:28:52


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