IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Akira Onozawa (NTT)
Vice Chair Kimiyoshi Usami (Shibaura Inst. of Tech.)
Secretary Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.)

Technical Committee on Component Parts and Materials (CPM) [schedule] [select]
Chair Kanji Yasui (Nagaoka Univ. of Tech.)
Vice Chair Yasushi Takemura (Yokohama National Univ.)
Secretary Tadayuki Imai (NTT), Satoru Noge (Numazu National College of Tech.)
Assistant Toshishige Shimamura (NTT), Katsuya Abe (Shinshu Univ.)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Kunio Uchiyama (Hitachi)
Vice Chair Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI)
Secretary Yoshio Hirose (Fujitsu Labs.), Hiroaki Suzuki (Renesas)
Assistant Toshimasa Matsuoka (Osaka Univ.), Ken Takeuchi (Univ. of Tokyo), Kenichi Okada (Tokyo Inst. of Tech.)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Shuichi Sakai (Univ. of Tokyo)
Vice Chair Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.)
Secretary Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC)
Assistant Hidetsugu Irie (Univ. of Electro-Comm.)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Tomohiro Yoneda (NII)
Vice Chair Seiji Kajihara (Kyushu Inst. of Tech.)
Secretary Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Akira Nagoya (Okayama Univ.)
Vice Chair Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary Yohei Hori (AIST), Tomonori Izumi (Ritsumeikan Univ.)
Assistant Nobuya Watanabe (Okayama Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Kazutoshi Wakabayashi
Secretary Naoyuki Hoshi, Naohito Kojima, Kenshu Seto

Conference Date Mon, Nov 29, 2010 10:40 - 18:00
Tue, Nov 30, 2010 09:10 - 18:15
Wed, Dec 1, 2010 09:10 - 15:50
Topics Design Gaia 2010 ―New Field of VLSI Design― 
Conference Place Centennial Hall Kyushu University School of Medicine 
Transportation Guide http://www.med.kyushu-u.ac.jp/100ko-do/koutuu.htm
Contact
Person
Prof. Tohru Ishihara
+81-92-847-5188
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Mon, Nov 29 AM 
10:40 - 12:00
(1)
ICD
10:40-11:00 Evaluation of frequency components of power noise in CMOS digital LSI CPM2010-124 ICD2010-83 Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST)
(2)
ICD
11:00-11:20 Evaluation of on-chip power noise generation and injection in SRAM core CPM2010-125 ICD2010-84 Takuya Sawada, Taku Toshikawa, Tsubasa Masui (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST)
(3)
ICD
11:20-11:40 A Consideration of Substrate Noise Sensitivity of Analog Elements CPM2010-126 ICD2010-85 Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.)
(4)
CPM
11:40-12:00 Evaluation of Signal-Integrity Improvement Capability of the Segmental Transmission Line
-- In Its Application to Lines Including Inductances --
CPM2010-127 ICD2010-86
Hiroki Shimada, Shohei Akita, Masami Ishiguro, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba), Ikuo Yoshihara (Univ. of Miyazaki)
Mon, Nov 29 PM 
13:30 - 14:50
(5) 13:30-14:10 [Invited Talk]
Problems of on-chip interconnection and optical interconnection CPM2010-128 ICD2010-87
Shin Yokoyama, Yoshiteru Amemiya (Hiroshima Univ.)
(6) 14:10-14:50 [Invited Talk]
Present Status and Target Issue of LSI-Chip Optical Interconnection CPM2010-129 ICD2010-88
Keishi Ohashi (MIRAI-Selete/NEC), Tohru Mogami (MIRAI-Selete)
  14:50-15:00 Break ( 10 min. )
Mon, Nov 29 PM 
15:00 - 16:20
(7) 15:00-15:40 [Invited Talk]
Research Trends and Future Directions for Optical Interconnects Technologies CPM2010-130 ICD2010-89
Toshiki Sugawara, Yasunobu Matsuoka, Shin-ichi Saito, Naoki Matsushima, Shinji Tsuji (Hitachi)
(8) 15:40-16:20 [Invited Talk]
Trend of the ESD design technology of the advanced semiconductor devices
Hiroyasu Ishizuka (Renesas)
  16:20-16:30 Break ( 10 min. )
Mon, Nov 29 PM 
16:30 - 18:00
(9) 16:30-18:00 Panel Discussion
Mon, Nov 29 PM 
13:30 - 15:10
(10)
VLD
13:30-13:50 An Approach to Translate from Mathematical to Electronic Descriptions of Image Processing Algorithm for ITS VLD2010-57 DC2010-24 Yukio Fujita, Masanori Tsuzuki, Yoshiya Sugita, Masahiro Fukui (Ritsumeikan Univ.)
(11)
VLD
13:50-14:10 Rapid SoC Prototyping Based on Virtual Multi-Processor Model VLD2010-58 DC2010-25 Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
(12)
VLD
14:10-14:30 A Scalable Heuristic for Incremental High-Level Synthesis VLD2010-59 DC2010-26 Shohei Ono (Univ. Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
(13) 14:30-14:50  
(14)
DC
14:50-15:10 A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths VLD2010-60 DC2010-27 Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
  15:10-15:25 Break ( 15 min. )
Mon, Nov 29 PM 
15:25 - 17:05
(15)
DC
15:25-15:45 Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure VLD2010-61 DC2010-28 Hisato Yamaguchi, Makoto Matsuzono, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech./JST)
(16)
DC
15:45-16:05 A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation VLD2010-62 DC2010-29 Yang Shen, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ)
(17)
DC
16:05-16:25 Rotating Test and Pattern Partitioning for Field Test Senling Wang, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Insti. Tech.)
(18)
DC
16:25-16:45 Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders VLD2010-63 DC2010-30 Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(19) 16:45-17:05  
Tue, Nov 30 AM 
09:10 - 10:10
(20)
ICD
09:10-09:30 17 Gb/s VCSEL Driver Using Double-Pulse Asymmetric Emphasis Technique for Optical Interconnection CPM2010-131 ICD2010-90 Takaya Taniguchi, Kiichi Yamashita, Kenichi Ohhata (Kagoshima Univ.), Norio Chujo, Toru Yazaki (Hitachi)
(21)
ICD
09:30-09:50 Improvement and Evaluation of via programmable structured ASIC VPEX CPM2010-132 ICD2010-91 Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(22)
ICD
09:50-10:10 An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array CPM2010-133 ICD2010-92 Amarjargal Gundjalam, Minoru Watanabe (Shizuoka Univ.)
  10:10-10:25 Break ( 15 min. )
Tue, Nov 30 AM 
10:25 - 11:45
(23) 10:25-11:05 [Invited Talk]
System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology CPM2010-134 ICD2010-93
Masahiro Aoyagi (AIST)
(24) 11:05-11:45 [Invited Talk]
A wafer-level system integration technology for heterogeneous devices with pseudo-SoC CPM2010-135 ICD2010-94
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R&D Center)
Tue, Nov 30 AM 
09:30 - 10:30
(25)
VLD
09:30-09:50 Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy VLD2010-64 DC2010-31 Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.)
(26)
VLD
09:50-10:10 Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors VLD2010-65 DC2010-32 Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)
(27)
VLD
10:10-10:30 A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes VLD2010-66 DC2010-33 Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.)
  10:30-10:45 Break ( 15 min. )
Tue, Nov 30 AM 
10:45 - 11:45
(28)
VLD
10:45-11:05 FPGA design and test methodology for communication frame processinng VLD2010-67 DC2010-34 Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT)
(29)
VLD
11:05-11:25 Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes VLD2010-68 DC2010-35 Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
(30) 11:25-11:45  
Tue, Nov 30 PM 
13:15 - 14:35
(31)
CPSY
13:15-13:35 A case study of the effective value range analysis for Behavioral synthesis CPSY2010-32 Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(32)
CPSY
13:35-13:55 Examination of the virtual wiring for an ASIC emulator using high-speed serial communication CPSY2010-33 Toshio Yabuta, Yoshihiro Ichinomiya, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(33)
CPSY
13:55-14:15 A Router Architecture for Priority-Aware On-Chip Networks CPSY2010-34 Takuma Kogo, Nobuyuki Yamasaki (Keio Univ)
(34)
CPSY
14:15-14:35 A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU CPSY2010-35 Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
Tue, Nov 30 PM 
13:15 - 14:55
(35)
RECONF
13:15-13:35 Circuit Generation using High-Level Synthesis Tool in Reconfigurable HPC System Based on FPGA Arrays RECONF2010-39 Kenichi Takahashi, Jiang Li, Hiroki Isogai, Hiroki Banba, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(36)
RECONF
13:35-13:55 OS Functions for a Distributed FPGA Cluster System using Ethernet RECONF2010-40 Akira Kojima, Takahiro Kajiyama, Tetsuo Hironaka (Hiroshima City Univ.)
(37)
RECONF
13:55-14:15 On a Prefetching Heterogeneous MDD Machine RECONF2010-41 Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)
(38)
RECONF
14:15-14:35 An FPGA Implementation of CRC Slicing-by-N algorithms RECONF2010-42 Amila Akagic, Hideharu Amano (Keio Univ.)
(39)
RECONF
14:35-14:55 A case study of efficient task scheduling for FPGA-based partially reconfigurable systems RECONF2010-43 Yoshiaki Tsutsumi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
Tue, Nov 30 PM 
13:15 - 14:15
(40) 13:15-14:15 [Invited Talk]
Paper Writing Guide for International Conferences
-- Implications in VLSI design methodology field --
VLD2010-69 DC2010-36
Masanori Hashimoto (Osaka Univ.)
Tue, Nov 30 PM 
14:15 - 14:55
(41)
VLD
14:15-14:35 Accurate Delay Analysis Method of Power-Gated Circuit VLD2010-70 DC2010-37 Seidai Takeda, Kim Kyundong, Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.)
(42) 14:35-14:55  
Tue, Nov 30 PM 
15:30 - 17:00
(43) 15:30-17:00  
  17:00-17:15 Break ( 15 min. )
Tue, Nov 30 PM 
17:15 - 18:15
(44) 17:15-18:15 [Invited Talk]
Photonic-electronic Convergence Technology Based on Silicon
-- Integration of photomic and electric circuits utilizing Siliconphotonics --
VLD2010-71 DC2010-38
Seiichi Itabashi, Tai Tsuchizawa, Koji Yamada, Toshifumi Watanabe, Hiroyuki Shinojima, Hidetaka Nishi, Rei Takahashi (NTT Corp.), Kazumi Wada, Yasuhiko Ishikawa (Univ. of Tokyo.)
Wed, Dec 1 AM 
09:30 - 10:30
(45)
CPSY
09:30-09:50 A Study of Comparison between In-order and Out-of-order Processor for Many-core Processor Era CPSY2010-36 Takefumi Miyoshi, Hidetsugu Irie, Yuuki Matsumura, Tsutomu Yoshinaga (UEC)
(46)
CPSY
09:50-10:10 Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis CPSY2010-37 Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
(47)
CPSY
10:10-10:30 Reliable Digital Signal Transmission Methodology
-- Its Application to the High Speed Bass Line --
CPSY2010-38
Shohei Akita, Hiroki Shimada, Masami Ishiguro, Noriyuki Aibe, Moritoshi Yasunaga (Univ. of Tsukuba), Ikuo Yoshihara (Miyazaki Univ.)
Wed, Dec 1 AM 
09:30 - 10:30
(48)
RECONF
09:30-09:50 Power-Consumption-Evaluation on the Pattern-Recognition Machine Using Data-Direct-Implementation Approach RECONF2010-44 Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba)
(49)
RECONF
09:50-10:10 Fabrication in Low Power Process and Evaluation of Power Reconfigurable Field Programmable Gate Array RECONF2010-45 Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yohei Matsumoto (TUMSAT), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
(50)
RECONF
10:10-10:30 Magnetic Field Measurement for Side-channel Analysis Environment RECONF2010-46 Toshihiro Katashita, Yohei Hori, Akashi Satoh (AIST)
  10:30-10:45 Break ( 15 min. )
Wed, Dec 1 AM 
10:45 - 11:45
(51)
RECONF
10:45-11:05 An Effective Processing Method for Parallel Loops on FPGA with PCI-Express RECONF2010-47 Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST)
(52)
RECONF
11:05-11:25 A study of the success rate of MIA under various probability density function estimations RECONF2010-48 Yohei Hori (AIST), Takahiro Yoshida (Aoyama Univ.), Toshihiro Katashita, Akashi Satoh (AIST)
(53)
RECONF
11:25-11:45 Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing RECONF2010-49 Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST)
Wed, Dec 1 AM 
09:10 - 10:30
(54)
DC
09:10-09:30 SREEP: A Tool for Secure Scan Design Using Shift Register Equivalents VLD2010-72 DC2010-39 Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.)
(55) 09:30-09:50  
(56)
DC
09:50-10:10 Fault-Injection using Virtualized Environment for Validating Automotive Systems VLD2010-73 DC2010-40 Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.)
(57)
DC
10:10-10:30 Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme VLD2010-74 DC2010-41 Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST)
  10:30-10:45 Break ( 15 min. )
Wed, Dec 1 AM 
10:45 - 11:45
(58)
VLD
10:45-11:05 ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding VLD2010-75 DC2010-42 Mineo Kaneko (JAIST)
(59) 11:05-11:25  
(60)
DC
11:25-11:45 A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description VLD2010-76 DC2010-43 Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST)
Wed, Dec 1 PM 
13:15 - 13:55
(61)
RECONF
13:15-13:55 [Invited Talk]
Monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS RECONF2010-50
Tatasuya Naito, Tatsuya Ishida (Toshiba), Takeshi Onoduka (Covalent Materials), Masahito Nishigoori, Takeo Nakayama, Yoshihiro Ueno, Yasumi Ishimoto, Akihiro Suzuki, Chung Weicheng (Toshiba), Raminda Madurawe (readyASIC), Sheldon Wu (China International Intellectual Property Services), Shu Ikeda (tei Solutions), Hisato Oyamatsu (Toshiba)
  13:55-14:10 Break ( 15 min. )
Wed, Dec 1 PM 
14:10 - 14:50
(62)
RECONF
14:10-14:30 An FPGA Implementation of Face Detection Recognition System for automobile using Impulse C RECONF2010-51 Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.)
(63)
RECONF
14:30-14:50 FPGA Accelaration Default Intensity Model RECONF2010-52 Takaaki Yokoyama, Hideharu Amano (Keio Univ.)
Wed, Dec 1 PM 
13:15 - 14:35
(64)
VLD
13:15-13:35 Adjacent Insertion and Its Effectiveness in Code-Based 3-D Placement VLD2010-77 DC2010-44 Shin Uesugi, Mineo Kaneko (JAIST)
(65)
VLD
13:35-13:55 On pruning rules in exact algorithms for the minimum rectilinear Steiner arborescence problem VLD2010-78 DC2010-45 Masayuki Nagase, Toshihiko Takahashi (Niigat Univ.)
(66)
VLD
13:55-14:15 Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications VLD2010-79 DC2010-46 Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
(67)
VLD
14:15-14:35 Develop A Clock Tree Generator into Open-source CAD System. VLD2010-80 DC2010-47 Takuya Higuchi, Jun'ichiro Ogane, Naohiko Shimizu (Tokai Univ.)
  14:35-14:50 Break ( 15 min. )
Wed, Dec 1 PM 
14:50 - 15:50
(68)
VLD
14:50-15:10 Optimal adder architecture in ultra low voltage domain VLD2010-81 DC2010-48 Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.)
(69)
VLD
15:10-15:30 A proposal for VLSI model for evaluation of rush current by power gating VLD2010-82 DC2010-49 Hiroto Yamaguchi, Junki Miyajima, Tomohiko Sumi, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
(70)
VLD
15:30-15:50 Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control VLD2010-83 DC2010-50 Xin Man (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Tomoo Kimura, Koji Kai (Panasonic), Shinji Kimura (Waseda Univ.)

Announcement for Speakers
General TalkEach speech will have 15 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Akihisa Yamada (Sharp)
E-: asrp
Tel: +81-743-65-2501, Fax: +81-743-65-0554 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPM Technical Committee on Component Parts and Materials (CPM)   [Latest Schedule]
Contact Address Toshishige Shimamura(NTT Microsystem Integration Laboratories)
3-1, Morinosato Wakamiya, Atsugi, Kanagawa 243-0198 Japan
TEL +81-46-240-2415 FAX +81-46-240-2936
E-:taecl 
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Toshimasa Matsuoka (Osaka University)
TEL 06-6879-7792,FAX 06-6879-7792
E-:eeieng-u 
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Morihiro KUGA (Kumamoto Univ.)
TEL +81-96-342-3647, FAX +81-96-342-3599
E-: am-u 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masato Kitakami
Graduate School of Advanced Integration Science,
Chiba University
1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN
TEL/FAX +43.290.3039
E-:fultyba-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Nobuya WATANABE (Okayama Univ.)
E-: bu-u
TEL: +81-86-251-8251
FAX: +81-86-251-8251 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  


Last modified: 2010-11-26 18:52:14


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to VLD Schedule Page]   /   [Return to CPM Schedule Page]   /   [Return to ICD Schedule Page]   /   [Return to CPSY Schedule Page]   /   [Return to DC Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan