IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nagisa Ishiura (Kwansei Gakuin Univ.)
Vice Chair Kazutoshi Wakabayashi (NEC)
Secretary Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Toshinori Sueyoshi (Kumamoto Univ.)
Vice Chair Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi)
Secretary Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.)
Assistant Hidetsugu Irie (Univ. of Tokyo)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Kazuhiko Iwasaki (Tokyo Metropolitan Univ.)
Vice Chair Tomohiro Yoneda (NII)
Secretary Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Hideharu Amano (Keio Univ.)
Vice Chair Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.)
Secretary Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Assistant Yohei Hori (AIST)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Hidetoshi Onodera
Secretary Isaro Utsumi, Yutaka Tamiya, Tohru Ishihara

Special Interest Group on Computer Architecture (IPSJ-ARC) [schedule] [select]

Conference Date Tue, Nov 20, 2007 10:05 - 17:15
Wed, Nov 21, 2007 13:00 - 17:00
Thu, Nov 22, 2007 09:00 - 16:10
Topics Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Conference Place  
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Tue, Nov 20 AM 
10:05 - 11:45
(1)
DC
10:05-10:30 2-Step Test Data Compression using Scan FF with Two Pattern Testability VLD2007-70 DC2007-25 Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.)
(2)
DC
10:30-10:55 A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing VLD2007-71 DC2007-26 Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT)
(3)
DC
10:55-11:20 An optimization of thru trees for test generation based on acyclical testability VLD2007-72 DC2007-27 Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(4)
IPSJ-SLDM
11:20-11:45 An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.)
Tue, Nov 20 AM 
10:05 - 11:45
(5)
IPSJ-SLDM
10:05-10:30 A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
(6)
IPSJ-SLDM
10:30-10:55 An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
(7)
VLD
10:55-11:20 A process-variation-aware low-power technique using current control VLD2007-76 DC2007-31 Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo)
(8)
VLD
11:20-11:45 Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit VLD2007-77 DC2007-32 Yoshinobu Toyoda, Kenta Kido, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.)
  11:45-12:00 Break ( 15 min. )
  12:00-15:00 Poster Session (Event Hall) ( 180 min. )
  15:00-15:10 Break ( 10 min. )
Tue, Nov 20 PM  CPSY: Design and Verification for Computer Systems
15:10 - 17:15
(9)
CPSY
15:10-15:35 A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs CPSY2007-35 Daisuke Hayashi, Wataru Murai (Osaka Univ.), Akio Nakata (Hiroshima City Univ.), Tomoya Kitani, Keiichi Yasumoto (NAIST), Teruo Higashino (Osaka Univ.)
(10)
CPSY
15:35-16:00 Development of Inter-module Communication Mechanism for Dynamically Reconfigurable System CPSY2007-36 Tomoyuki Ishida, Taiichiro Yatsunami, Osamu Kawaguchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(11)
CPSY
16:00-16:25 KNIVES: Internet Based Distributed Shared Demand Side Management System CPSY2007-37 Akihiro Oda, Tomokazu Tachikawa, Tomohiko Handa (Keio Univ.), Junichi Ichimura (Tokyo Gas Ltd.), Hiroaki Nishi (Keio Univ.)
(12)
CPSY
16:25-16:50 FTN Simulation Technology Based on Analysis of Frequency, Time and Noise for High-speed Serial Communication System CPSY2007-38 Goichi Ono, Takashi Takemoto, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi)
(13)
CPSY
16:50-17:15 The Evaluation of High-speed Serial Communication System by Using FTN Simulation Technology CPSY2007-39 Takashi Takemoto, Goichi Ono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi)
Tue, Nov 20 PM  RECONF: Reconfigurable Systems 1 (Room 21)
15:10 - 16:50
(14)
RECONF
15:10-15:35 A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture RECONF2007-32 Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)
(15)
RECONF
15:35-16:00 A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell RECONF2007-33 Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(16)
RECONF
16:00-16:25 Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield RECONF2007-34 Yuuri Sugihara, Youhei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
(17)
RECONF
16:25-16:50 Retrieving 3D infomation with streamed template matching RECONF2007-35 Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
Tue, Nov 20 PM 
15:10 - 16:50
(18)
DC
15:10-15:35 Comparison of Standard Cell Non-linear Asynchronous Pipelines VLD2007-78 DC2007-33 Chammika Mannakkara, Tomohiro Yoneda (NII)
(19)
IPSJ-SLDM
15:35-16:00 An On-Chip Bus Architecture for Post-Fabrication Timing Calibration Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
(20)
VLD
16:00-16:25 Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing VLD2007-80 DC2007-35 Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.)
(21)
VLD
16:25-16:50 Initial Evaluation of FIR Filter Based on Digit-Serial Computation VLD2007-81 DC2007-36 Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
Wed, Nov 21 PM 
13:00 - 14:00
(22) 13:00-14:00 [Fellow Memorial Lecture]
Social Information Infrastructure and Dependable VLSI VLD2007-82 DC2007-37 RECONF2007-36
Hiroto Yasuura (Kyushu Univ.)
  14:00-14:15 Break ( 15 min. )
Wed, Nov 21 PM  RECONF: Dynamic Reconfiguration (Room 21)
14:15 - 15:30
(23)
RECONF
14:15-14:40 The technical comparison of Digital Media Processor and Dynamically Reconfigurable Processor RECONF2007-37 Kazuo Yamada, Takao Naito (Fuji Xerox)
(24)
RECONF
14:40-15:05 An approach to Place and Route challenges in Dynamic Reconfiguration RECONF2007-38 Ryo Hidaka, Fuminori Kobayashi (Kyushu Inst. of Tech.), Minoru Watanabe (Shizuoka Univ.)
(25)
RECONF
15:05-15:30 Redusing Overhead of transferring configuration data on Dynamically Reconfigurable Processor MuCCRA RECONF2007-39 Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)
Wed, Nov 21 PM 
14:15 - 15:30
(26)
DC
14:15-14:40 A design method for easily testable multipliers adaptable to various structures of partial product addition VLD2007-83 DC2007-38 Nobutaka Kito, Naofumi Takagi (Nagoya Univ.)
(27)
DC
14:40-15:05 Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning VLD2007-84 DC2007-39 Thomas Edison Yu, Tomokazu Yoneda (NAIST), Krishnendu Chakrabarty (Duke Univ.), Hideo Fujiwara (NAIST)
(28)
DC
15:05-15:30 A Construction Method of Path Delay Fault Detectable Circuits VLD2007-85 DC2007-40 Takashi Watanabe, Takeo Yoshida (Univ. of the Ryukyus)
  15:30-15:45 Break ( 15 min. )
Wed, Nov 21 PM  RECONF: Low-power Techniques (Room 21)
15:45 - 17:00
(29)
RECONF
15:45-16:10 Architecture Exploration Method for Low-Power Dynamically Reconfigurable Processors RECONF2007-40 Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbungheng, Hideharu Amano (Keio Univ.)
(30)
RECONF
16:10-16:35 Power analysis on Dynamic Reconfigurable Processor RECONF2007-41 Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)
(31)
RECONF
16:35-17:00 A low power consumption processor with on-chip control mechanism using pipeline stage unification RECONF2007-42 Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.)
Wed, Nov 21 PM 
15:45 - 17:00
(32)
VLD
15:45-16:10 A Resource Binding Method for Reducing Power Consumption of LSI Data Communications VLD2007-86 DC2007-41 Hidekazu Seto, Kazuhito Ito (Saitama Univ.)
(33)
VLD
16:10-16:35 Design of low energy array multipliers by reducing signal transitions in partial product accumulators VLD2007-87 DC2007-42 Hirotaka Kawashima, Kazuhiro Nakamura, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.)
(34)
VLD
16:35-17:00 A power masking multiplying circuit based on galois field for composite field AES VLD2007-88 DC2007-43 Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
Thu, Nov 22 AM  RECONF: Reconfigurable Systems 2 (Room 21)
09:00 - 10:15
(35)
RECONF
09:00-09:25 Designing Soft Error Tolerant LUTs of SRAM-based FPGAs RECONF2007-43 Kohei Satoyama, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST)
(36)
RECONF
09:25-09:50 Performance evaluation of reconfigurable architecture based on digit-serial computation RECONF2007-44 Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
(37)
RECONF
09:50-10:15 An Implementation of Operating System Functions for a Reconfigurable System RECONF2007-45 Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.)
Thu, Nov 22 AM 
09:00 - 10:15
(38)
IPSJ-SLDM
09:00-09:25 Comparison between STA and SSTA results in microprocessor design Noriyuki Ito, Hiroaki Komatsu, Hiroyuki Sugiyama, Naomi Bizen, Katsumi Iguchi, Yuji Yoshida (Fujitsu)
(39)
VLD
09:25-09:50 A New Technique for Elimination of Irregular Data in Measured Values
-- A Data Screening Technique Appling Skewness of Basic Statistic --
VLD2007-90 DC2007-45
Shin-ichi Ohkawa, Hiroo Masuda (Renesas)
(40)
VLD
09:50-10:15 A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA VLD2007-91 DC2007-46 Shinyu Ninomiya, Masanori Hashimoto (Osaka Univ.)
  10:15-10:30 Break ( 15 min. )
Thu, Nov 22 AM  RECONF: Coding and Arithmetics (Room 21)
10:30 - 11:45
(41)
RECONF
10:30-10:55 A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism RECONF2007-46 Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(42)
RECONF
10:55-11:20 Proposal of Optimization Design System for LDPC using FPGA RECONF2007-47 Yukari Ishida, Hirotaka Nosato (Toho Univ.), Yosuke Iijima (Univ. of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST)
(43)
RECONF
11:20-11:45 Design Methods for Radix Converters (4)
-- RNS to Binary Conversion --
RECONF2007-48
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao (Kyutech)
Thu, Nov 22 AM 
10:30 - 11:45
(44)
VLD
10:30-10:55 Highly Extensible Base Processors for Short-term ASIP Design VLD2007-92 DC2007-47 Hirofumi Iwato, Takuji Hieda, Hiroaki Tanaka (Osaka Univ.), Jun Sato (Tsuruoka NCT), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
(45)
VLD
10:55-11:20 Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis VLD2007-93 DC2007-48 Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
(46)
VLD
11:20-11:45 A Schedule Improvement with Skew Control in Datapath Synthesis VLD2007-94 DC2007-49 Takayuki Obata, Mineo Kaneko (JAIST)
  11:45-13:00 Lunch Break ( 75 min. )
Thu, Nov 22 PM  RECONF: Applications (Room 21)
13:00 - 14:15
(47)
RECONF
13:00-13:25 Proposal for High-Speed Secure Network System using FPGA RECONF2007-49 Hirotaka Nosato, Yukari Ishida (Toho Univ.), Yosuke Iijima (Univ. of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST)
(48)
RECONF
13:25-13:50 Evaluation of a Data-Driven Architecture for a Stochastic Biochemical Simulator on an FPGA RECONF2007-50 Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Yuichiro Shibata, Hideki Yamada (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
(49)
RECONF
13:50-14:15 A Study on General Purpose Self-Organizing Map Hardware Accelerator Hiroshi Araki, Masato Yoshimi, Yasunori Osana, Hideharu Amano (Keio Univ.)
Thu, Nov 22 PM 
13:00 - 14:40
(50)
IPSJ-SLDM
13:00-13:25 Necessary and Sufficient Conditions for Symmetry Placements Kunihiro Fujiyoshi, Chikaaki Kodama, Shinichi Koda (TUAT)
(51)
VLD
13:25-13:50 Improved Method of Rectilinear Block Packing Based on O-Tree Representation VLD2007-96 DC2007-51 Hidehiko Ukibe, Kunihiro Fujiyoshi (TUAT)
(52)
IPSJ-SLDM
13:50-14:15 Parallel prefix adder synthesis based on Ling’s carry computation Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.)
(53)
VLD
14:15-14:40 An Efficient Behavioral Synthesis Method Considering Specialized Functional Units VLD2007-98 DC2007-53 Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.)
  14:40-14:55 Break ( 15 min. )
Thu, Nov 22 PM 
14:30 - 15:45
(54)
VLD
14:30-14:55 A Hardware Engine for Generation Deformed Map VLD2007-99 DC2007-54 Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(55)
VLD
14:55-15:20 An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems VLD2007-100 DC2007-55 Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus)
(56)
IPSJ-SLDM
15:20-15:45 Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
Thu, Nov 22 PM 
14:55 - 16:10
(57)
VLD
14:55-15:20 Cycle Partitioned Scheduling for Code Optimization of VLIW DSP VLD2007-102 DC2007-57 Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.)
(58)
VLD
15:20-15:45 Retargetable Linear Assembler for VLIW Processor VLD2007-103 DC2007-58 Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.)
(59)
VLD
15:45-16:10 Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor VLD2007-104 DC2007-59 Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Hiroyuki OCHI (Kyoto Univ.)
E-:oeek-u
Tel.075-753-4803 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Morihiro KUGA (Kumamoto Univ.)
TEL +81-96-342-3647, FAX +81-96-342-3599
E-: am-u 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masato Kitakami
Graduate School of Integration Science,
Chiba University
1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN
TEL/FAX +42.290.3269
E-:fultyba-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Yohei HORI (AIST)
E-: yaist
TEL: +81-29-861-5080 (Ext.)55459
FAX: +81-29-861-5909 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  
IPSJ-ARC Special Interest Group on Computer Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  


Last modified: 2007-11-15 15:41:00


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to VLD Schedule Page]   /   [Return to CPSY Schedule Page]   /   [Return to DC Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /   [Return to IPSJ-ARC Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan