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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Yusuke Matsunaga (Kyushu Univ.)
Vice Chair Takashi Takenana (NEC)
Secretary Hiroyuki Tomiyama (Ritsumeikan Univ.), Daisuke Fukuda (Fujitsu Labs.)
Assistant Ittetsu Taniguchi (Ritsumeikan Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Masahiro Fukui (Ritsumeikan Univ.)
Secretary Masao Yokoyama (Sharp), Yasuhiro Takashima (Kitakyushu City Univ.), Takeo Nishide (Toshiba)

Conference Date Wed, May 11, 2016 10:00 - 17:00
Topics System Design, etc. 
Conference Place  
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and
reproduction
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Wed, May 11 AM 
10:00 - 11:40
(1)
VLD
10:00-10:25 An Application of Subgradient Method to Delay Analysis VLD2016-1 Hiroshi Miyashita, Koutaro Kawaraguchi (The Univ. of Kitakyushu)
(2)
VLD
10:25-10:50 Self-Aligned Double Patterning-Aware Two-color Grid Routing VLD2016-2 Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT)
(3) 10:50-11:15  
(4) 11:15-11:40  
  11:40-13:00 Lunch Break ( 80 min. )
Wed, May 11 PM 
13:00 - 14:15
(5) 13:00-13:25  
(6) 13:25-13:50  
(7)
VLD
13:50-14:15 Multi bit soft error tolerant FPGA architecture VLD2016-3 Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
  14:15-14:30 Break ( 15 min. )
Wed, May 11 PM 
14:30 - 15:45
(8)
VLD
14:30-14:55 A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures VLD2016-4 Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(9)
VLD
14:55-15:20 A Note on Scheduling Problem Considering the Radiation Resistance of Registers Keisuke Inoue (KTC), Mineo Kaneko (JAIST)
(10)
VLD
15:20-15:45 MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA VLD2016-5 Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.)
  15:45-16:00 Break ( 15 min. )
Wed, May 11 PM 
16:00 - 17:00
(11)
VLD
16:00-17:00 [Invited Talk]
Challenges of DA Technologies for the Future
-- For the Establishment of Next Generation DA Technologies --
VLD2016-6
Michiaki Muraoka (Kochi Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Hiroyuki Tomiyama (Ritsumeikan University)
E-: htfci
Phone: 077-561-4928 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Yasuhiro Takashima (University of Kitakyushu)
E sldm2015isenvk-u 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2016-04-06 08:17:25


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