IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nagisa Ishiura (Kwansei Gakuin Univ.)
Vice Chair Kazutoshi Wakabayashi (NEC)
Secretary Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Toshinori Sueyoshi (Kumamoto Univ.)
Vice Chair Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi)
Secretary Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.)
Assistant Hidetsugu Irie (Univ. of Tokyo)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Hideharu Amano (Keio Univ.)
Vice Chair Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.)
Secretary Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Assistant Yohei Hori (AIST)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Hidetoshi Onodera
Secretary Isaro Utsumi, Yutaka Tamiya, Tohru Ishihara

Conference Date Wed, Jan 16, 2008 10:15 - 18:15
Thu, Jan 17, 2008 08:40 - 18:05
Topics FPGA Applications, etc 
Conference Place  
Transportation Guide http://www.keio.ac.jp/english/about_keio/campus_info/hiyoshi2.html
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, Jan 16 PM 
10:15 - 11:05
(1) 10:15-11:05 [Invited Talk]
Flex Power FPGA
Hanpei Koike (AIST)
  11:55-12:55 Lunch ( 60 min. )
Wed, Jan 16 PM 
12:55 - 14:35
(2) 12:55-13:20 High speed control system using Multilevel control circuit VLD2007-106 CPSY2007-49 RECONF2007-52 Hiroaki Maekawa, Ryuichi Tanaka, Masatoshi Sekine (TUAT)
(3) 13:20-13:45 Scalable RHPC(Reconfigurable HPC) by using FPGA array VLD2007-107 CPSY2007-50 RECONF2007-53 Hiroaki Iijima, Kazuki Sato, Masatoshi Sekine (Tokyo Univ. of Agriculture and Technology)
(4) 13:45-14:10 Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs VLD2007-108 CPSY2007-51 RECONF2007-54 Yuzo Nishioka, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(5) 14:10-14:35 An optimization method of DMA transfer for the SRC-6 reconfigurable machine VLD2007-109 CPSY2007-52 RECONF2007-55 Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
  14:35-14:45 Break ( 10 min. )
Wed, Jan 16 PM 
14:45 - 16:25
(6) 14:45-15:10 A study of the effectiveness of dynamic partial reconfiguration for size and power reduction VLD2007-110 CPSY2007-53 RECONF2007-56 Yohei Hori, Hirofumi Sakane, Kenji Toda (AIST)
(7) 15:10-15:35 Development of verification and power estimation methodology for circuits with Run Time Power Gating VLD2007-111 CPSY2007-54 RECONF2007-57 Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.)
(8) 15:35-16:00 Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating VLD2007-112 CPSY2007-55 RECONF2007-58 Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.)
(9) 16:00-16:25 An efficient algorithm for RTL power macro modeling and library building Masaaki Ohtsuki, Masato Kawai, Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.)
  16:25-16:35 Break ( 10 min. )
Wed, Jan 16 PM 
16:35 - 18:15
(10) 16:35-17:00 Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm VLD2007-114 CPSY2007-57 RECONF2007-60 Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
(11) 17:00-17:25 A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation VLD2007-115 CPSY2007-58 RECONF2007-61 Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
(12) 17:25-17:50 Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2 VLD2007-116 CPSY2007-59 RECONF2007-62 Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex)
(13) 17:50-18:15 A Method of Design and Update for an Address Generator Using a Hybrid Method VLD2007-117 CPSY2007-60 RECONF2007-63 Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (K.I.T.)
Thu, Jan 17 AM 
08:40 - 10:05
(14) 08:40-09:15 [Invited Talk]
ICCAD summary report VLD2007-118 CPSY2007-61 RECONF2007-64
Yusuke Matsunaga (Kyushu Univ.)
(15) 09:15-09:40 A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures VLD2007-119 CPSY2007-62 RECONF2007-65 Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(16) 09:40-10:05 Scheduling and Memory Binding in High Level Synthesis for FPGAs VLD2007-120 CPSY2007-63 RECONF2007-66 Yuki Sagawa, Tsuyoshi Sadakata, Yusuke Matsunaga (Kyusyu Univ.)
  10:05-10:15 Break ( 10 min. )
Thu, Jan 17 AM 
10:15 - 11:55
(17) 10:15-10:40 Improvement in data communication between PEs for SIMD type processor MX core VLD2007-121 CPSY2007-64 RECONF2007-67 Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
(18) 10:40-11:05 Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation VLD2007-122 CPSY2007-65 RECONF2007-68 Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.)
(19) 11:05-11:30 Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication VLD2007-123 CPSY2007-66 RECONF2007-69 Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.)
(20) 11:30-11:55 An effective data I/O mechanism utilizing FIFOs for an array processor VLD2007-124 CPSY2007-67 RECONF2007-70 Yuusuke Nomoto, Yuka Sato, Toshiaki Miyazaki (Univ. of Aizu)
  11:55-12:55 Break ( 60 min. )
Thu, Jan 17 PM 
12:55 - 15:25
(21) 12:55-13:20 Analysis of retention time under continuous reconfiguration of a DORGA VLD2007-125 CPSY2007-68 RECONF2007-71 Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
(22) 13:20-13:45 A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array VLD2007-126 CPSY2007-69 RECONF2007-72 Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
(23) 13:45-14:10 Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays. VLD2007-127 CPSY2007-70 RECONF2007-73 Kouji Shinohara, Minoru Watanabe (Shizuoka Univ.)
(24) 14:10-14:35 A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability VLD2007-128 CPSY2007-71 RECONF2007-74 Shin'ichi Kouyama, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.)
(25) 14:35-15:00 Functionally-partitioned JPEG decoder for partial dynamic reconfiguration VLD2007-129 CPSY2007-72 RECONF2007-75 Taiichiro Yatsunami, Hideaki Yoshihiro, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(26) 15:00-15:25 A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor VLD2007-130 CPSY2007-73 RECONF2007-76 Vu Manh Tuan, Hideharu Amano (Keio Univ.)
  15:25-15:35 Break ( 10 min. )
Thu, Jan 17 PM 
15:35 - 18:05
(27) 15:35-16:00 An L1 Data Cache Optimization Algorithm for Application Processor Cores VLD2007-131 CPSY2007-74 RECONF2007-77 Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(28) 16:00-16:25 A Processor Kernel Generation Method for Application Processors VLD2007-132 CPSY2007-75 RECONF2007-78 Toshihiro Hiura, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(29) 16:25-16:50 A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator VLD2007-133 CPSY2007-76 RECONF2007-79 Farhad Mehdipour (Kyushu Univ.), Hamid Noori (ISIT), Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
(30) 16:50-17:15 VLIW Extension of Software Development Environment Construction Tool ArchC VLD2007-134 CPSY2007-77 RECONF2007-80 Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.)
(31) 17:15-17:40 Hardware Consious Style: a C Language Style for Hardware Design VLD2007-135 CPSY2007-78 RECONF2007-81 Kaiyi Mao, Hideharu Amano, Satoshi Tsutsumi, Vasutan Tunbunheng (Keio Univ.)
(32) 17:40-18:05 C to HDL compiler for rapid HW-SW co-simulation models VLD2007-136 CPSY2007-79 RECONF2007-82 Yasuhiro Ito, Yutaka Sugawara, Kei Hiraki (Tokyo Univ.)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Hiroyuki OCHI (Kyoto Univ.)
E-:oeek-u
Tel.075-753-4803 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Morihiro KUGA (Kumamoto Univ.)
TEL +81-96-342-3647, FAX +81-96-342-3599
E-: am-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Yohei HORI (AIST)
E-: yaist
TEL: +81-29-861-5080 (Ext.)55459
FAX: +81-29-861-5909 
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  


Last modified: 2008-01-15 20:49:42


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
 
[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to VLD Schedule Page]   /   [Return to CPSY Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan