IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Hidetsugu Irie (Univ. of Tokyo)
Vice Chair Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.)
Secretary Shinya Takameda (Hokkaido Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)
Assistant Shugo Ogawa (Hitachi), Eiji Arima (Univ. of Tokyo)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Hiroshi Takahashi (Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Hiroshi Inoue (Kyushu Univ.)
Secretary Satoshi Imamura (Fujitsu Labs.), Ryota Shioya (Univ. of Tokyo), Teruo Tanimoto (Kyushu Univ.), Koyo Nitta (NTT)

Conference Date Thu, Jul 30, 2020 11:00 - 18:00
Fri, Jul 31, 2020 09:15 - 18:30
Topics SWoPP2020: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Conference Place  
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CPSY, DC.

Thu, Jul 30 AM 
11:00 - 12:30
11:00-11:30 Instruction Prefetcher focusing on properties of Prefetch Distance CPSY2020-1 DC2020-1 Tomoki Nakamura, Toru Koizumi, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya (UTokyo)
(2) 11:30-12:00  
(3) 12:00-12:30  
  12:30-13:30 Break ( 60 min. )
Thu, Jul 30 PM 
13:30 - 15:00
(4) 13:30-14:00  
(5) 14:00-14:30  
14:30-15:00 Distributed Runtime Environment with Julia Language CPSY2020-2 DC2020-2 Hidemoto Nakada (AIST)
  15:00-15:15 Break ( 15 min. )
Thu, Jul 30 PM 
15:15 - 16:45
15:15-15:45 CPSY2020-3 DC2020-3
15:45-16:15 Automated Fixed-Point Bit-Length Optimization for OS-ELM CPSY2020-4 DC2020-4 Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
16:15-16:45 Preliminary examination of normally-off power management for local 5G base station CPSY2020-5 DC2020-5 Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura (UTokyo)
  16:45-17:00 Break ( 15 min. )
Thu, Jul 30 PM 
17:00 - 18:00
17:00-17:30 Proposal for an IP-based Design Environment for CGRA Applications CPSY2020-6 DC2020-6 Ayaka Ohwada, Takuya Kojima, Hideharu Amano (Keio Univ.)
17:30-18:00 CPSY2020-7 DC2020-7 Takuya Kojima, Ayaka Ohwada, Hideharu Amano (Keio Univ.)
Fri, Jul 31 AM 
09:15 - 10:45
(12) 09:15-09:45  
09:45-10:15 A Case for Acceleration of 2D Graph-Based SLAM using FPGA CPSY2020-8 DC2020-8 Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
(14) 10:15-10:45  
  10:45-11:00 Break ( 15 min. )
Fri, Jul 31 AM 
11:00 - 12:30
11:00-11:30 The next generation FiC with M-KUBOS board CPSY2020-9 DC2020-9 Hideharu Amano, Kazuei Hironaka, Kensuke Iizuka (Keio Univ.)
11:30-12:00 Task Offloading of a Distributed and Cooperative Cache Server using FPGA CPSY2020-10 DC2020-10 Teppei Yamagishi (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
12:00-12:30 A study of an FPGA-based cluster computing with high-speed serial links CPSY2020-11 DC2020-11 Fan Ruochong, Ao Yun, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba)
  12:30-15:15 Break ( 165 min. )
Fri, Jul 31 PM 
15:15 - 16:45
(18) 15:15-15:45 (cancelled)
15:45-16:15 A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns CPSY2020-12 DC2020-12 Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)
16:15-16:45 A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount CPSY2020-13 DC2020-13 Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)
  16:45-17:00 Break ( 15 min. )
Fri, Jul 31 PM 
17:00 - 18:30
17:00-17:30 CPSY2020-14 DC2020-14 Daichi Minamide, Tatsuhiro Tsuchiya (Osaka Univ.)
17:30-18:00 An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation CPSY2020-15 DC2020-15 Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
18:00-18:30 A Study on Error Correction Coding For Matrix Multiplications Based On Product Codes CPSY2020-16 DC2020-16 Yuki Katsu, Haruhiko Kaneko (Titech)

Announcement for Speakers
General TalkEach speech will have 25 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address CPSY WEB 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E-: ain-u 
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  

Last modified: 2020-07-23 08:16:01

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
[Presentation and Participation FAQ] (in Japanese)
[Cover and Index of IEICE Technical Report by Issue]

[Return to CPSY Schedule Page]   /   [Return to DC Schedule Page]   /   [Return to IPSJ-ARC Schedule Page]   /  
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan