IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Michiko Inoue (NAIST)
Vice Chair Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Secretary Masayoshi Yoshimura (Kyoto Sangyo Univ.), Haruhiko Kaneko (Tokyo Inst. of Tech.)

Conference Date Tue, Feb 21, 2017 10:30 - 17:00
Topics VLSI Design and Test, etc 
Conference Place Kikai-Shinko-Kaikan Bldg. 
Contact
Person
Prof. Tomoo Inoue, Toshinori Hosokawa
+81-3-3434-8216
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Tue, Feb 21 AM  Low Power Testing
10:30 - 11:20
(1) 10:30-10:55 A dynamic test compaction method on low power oriented test generation using capture safe test vectors DC2016-74 Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.)
(2) 10:55-11:20 IR-Drop Analysis on Different Power Supply Network Designs DC2016-75 Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech)
  11:20-11:35 Break ( 15 min. )
Tue, Feb 21 AM  Fault Diagnosis
11:35 - 12:25
(3) 11:35-12:00 Built-In Self Diagnosis Architecture for Logic Design DC2016-76 Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Satoshi Ohtake (Oita Univ.)
(4) 12:00-12:25 An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination DC2016-77 Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design)
  12:25-14:00 Break ( 95 min. )
Tue, Feb 21 PM 
14:00 - 14:50
(5) 14:00-14:25 Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems DC2016-78 Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(6) 14:25-14:50 An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States DC2016-79 Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
  14:50-15:05 Break ( 15 min. )
Tue, Feb 21 PM 
15:05 - 15:55
(7) 15:05-15:30 A Method of Strongly Secure Scan Design Using Extended Shift Registers DC2016-80 Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ)
(8) 15:30-15:55 A Study of Message Efficient Avoidance Routing DC2016-81 Yusuke Sugiura, Tomoya Osuki, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
  15:55-16:10 Break ( 15 min. )
Tue, Feb 21 PM 
16:10 - 17:00
(9) 16:10-16:35 Considerations on Characteristics of Ring Oscillators Implemented in FPGA DC2016-82 Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.)
(10) 16:35-17:00 Design for Evaluation of TSV based Interconnections in 3D-SIC
-- Interconnection Resistance Evaluation with Analog Boundary Scan --
DC2016-83
Shuichi Kameyama (Ehime Univ./Fujitsu), Senling Wang, Hiroshi Takahashi (Ehime Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address  


Last modified: 2017-01-11 08:06:54


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to DC Schedule Page]   /  
 
 Go Top  Go Back   Prev DC Conf / Next DC Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan