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Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Masao Nakaya
Vice Chair Akira Matsuzawa
Secretary Shinji Miyano, Koji Kai
Assistant Yoshiharu Aimoto, Makoto Nagata

Conference Date Thu, May 25, 2006 10:30 - 16:45
Fri, May 26, 2006 10:30 - 16:45
Topics  
Conference Place KOBE Universary Centennial Hall 
Address 1-1, Rokkodai, Nada-ku Kobe 657-8501 Japan
Transportation Guide About 15-20 min. from Hankyu Railway "Rokko" Station by walk
http://www.kobe-u.ac.jp/en/info/access/rokko/index.htm
Contact
Person
Prof. Masahiko Yoshimoto
078-881-1212(大代表)

Thu, May 25 AM 
10:30 - 16:45
(1) 10:30-11:00 Circuits Technologies for Flexible Braille Sheet Display with Organic FETs and Plastic Actuators Hiroshi Kawaguchi (Kobe Univ.), Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Takao Someya, Takayasu Sakurai (Univ. of Tokyo)
(2) 11:00-11:30 1/1.8” 6.4M pixel 60frame/s CMOS Image Sensor Masaru Kikuchi, Satoshi Yoshihara (Sony), Ken Koseki (Sony LSI Design), Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano (Sony), Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima (Sony LSI Design), Tadashi Nakajima, Yoshiharu Kudo, Fumihiko Koga, Tetsuo Nomoto (Sony)
(3) 11:30-12:00 System-in-Silicon architecture and its application to a motion estimation engine Kouichi Kumagai (SFT), Changqi Yang (Waseda Univ.), Hitoshi Izumino, Nobuyuki Narita, Keisuke Shinjo, Shin-ichi Iwashita, Yuji Nakaoka, Tomohiro Kawamura, Hideo Komabashiri, Tsukasa Minato, Atsushi Ambo, Takamasa Suzuki (SFT), Zhenyu Liu, Yang Song, Satoshi Goto (Waseda Univ.)
  12:00-13:00 Lunch ( 60 min. )
(4) 13:00-13:30 A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips --
Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas)
(5) 13:30-14:00 Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL)
(6) 14:00-14:30 High-Speed Transceiver Circuit for a Multiprocessor Server Using Over 1Tb/s Crossbar Ryuichi Nishiyama, Souta Sakabayashi, Jun Yamada, Hiroyuki Adachi, Yutaka Mori (Fujitsu)
  14:30-14:45 Break ( 15 min. )
(7) 14:45-15:45 [Special Invited Talk]
Technological trend of advanced processsors pursuing high performance/watt
Kunio Uchiyama (Hitachi)
(8) 15:45-16:45 [Special Invited Talk]
Deep Sub-100nm Design Challenges
Tohru Furuyama (Toshiba)
Fri, May 26 PM 
10:30 - 16:45
(9) 10:30-11:00 A Digital Input Controller for Audio Class-D Amplifiers with 100W 0.004% THD+N and 113dB DR Toru Ido, Sonny Ishizuka (TIJ), Lars Risbo (TIDK), Fumitaka Aoyagi, Toshihiko Hamasaki (TIJ)
(10) 11:00-11:30 A 80/100 MS/s 76.3/70.1-dB SNDR ΔΣ ADC for digital TV receivers Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal LoRe, Masayuki Miyamoto (Sharp)
(11) 11:30-12:00 A 30mW 12b 50MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS. Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihede Ogawa (Sony LSI)
  12:00-13:00 Lunch ( 60 min. )
(12) 13:00-13:30 A PLL for a DVDx16 Write System with 63 Output Phases and 32ps Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie (Matsushita)
(13) 13:30-14:00 A 0.03mm2 9mW Wide-Range Duty-Cycle-Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi (Matsushita Electric), Makoto Hattori (PSCST)
(14) 14:00-14:30 An 18mW, 90 to 770MHz Synthesizer with Agile Auto-Tuning for Digital TV-tuners Masazumi Marutani, Hideaki Anbutsu, Masafumi Kondo, Noriaki Shirai, Hiroshi Yamazaki, Yuu Watanabe (Fujitsu)
  14:30-14:45 Break ( 15 min. )
(15) 14:45-15:15 1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe (Advantest)
(16) 15:15-15:45 A 1-ps Resolution Jitter Measurement Macro Using Interpolated Jitter Oversampling Koichi Nose, Mikihiro Kajita, Masayuki Mizuno (NEC)
(17) 15:45-16:15 A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu (Keio Univ.), Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi (NEC), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.)
(18) 16:15-16:45 A 20Gb/s Bidirectional Transceiver Using a Resister-Transconductor Hybrid Yasumoto Tomita (Keio Univ.), Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh (Fujitsu Laboratories LTD.), Tadahiro Kuroda (Keio Univ.)

Contact Address and Latest Schedule Information
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Makoto Nagata (Kobe University)
Tel:+81-78-803-6569 Fax:+81-78-803-6221
E-: be-u 


Last modified: 2006-04-06 00:44:14


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