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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Shinji Kimura
Vice Chair Hirofumi Hamamura
Secretary Yusuke Matsunaga, Toshiyuki Shibuya

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Masao Nakaya
Vice Chair Akira Matsuzawa
Secretary Shinji Miyano, Koji Kai
Assistant Yoshiharu Aimoto, Makoto Nagata

Conference Date Thu, Mar 9, 2006 09:15 - 16:50
Fri, Mar 10, 2006 09:15 - 16:25
Topics  
Conference Place  

Thu, Mar 9 AM 
09:15 - 10:30
(1) 09:15-09:40 Verifying Deep Bugs by Model Checking and Inductive Approach Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Tokyo Univ.)
(2) 09:40-10:05 An algorithm for power modeling and library building for system level design Katsuhiro Oshikawa, Masahiro Fukui (Rits)
(3) 10:05-10:30 An accurate static power analysis method which considers local switching activities Tatsuya Yamamoto, Yuu Yamashita, Katsuhiro Oshikawa, Masahiro Fukui (Rits)
  10:30-10:40 Break ( 10 min. )
Thu, Mar 9 AM 
10:40 - 11:55
(4) 10:40-11:05 A hardware/software partitioning system with design navigation for system LSIs Yohei Kojima, Nozomu Togawa (Waseda Univ.), Masayoshi Tachibana (Kouchi Univ. of Technology), Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(5) 11:05-11:30 Improved Network Processor for Dynamic Packet Flows and Its Experimental Evaluations Hidetaka Tabuchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(6) 11:30-11:55 Improvement of Clustering Based Clock Scheduling Method Yuuichi Sunahashiri, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech)
Thu, Mar 9 PM 
13:10 - 14:50
(7) 13:10-13:35 A Code Placement Technique for Power Minimization of Way-Predicting Caches Yohei Imai, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
(8) 13:35-14:00 A pipeline architecture optimization algorithm for SIMD-type processor core synthesis Akira Kurihara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(9) 14:00-14:25 Parallel CBM Algorithm and Architecture for JPEG 2000 Encoder for Digital Cinema Takeshi Ito, Takeshi Ikenaga (WASEDA Univ.), Sou Nakamura (FDI)
(10) 14:25-14:50 Investigation on high performance LDPC decoder for IEEE802.16e Ryota Gakiya, Tomohisa Wada (Univ. Ryukyu)
  14:50-15:10 Break ( 20 min. )
Thu, Mar 9 PM 
15:10 - 16:50
(11) 15:10-15:35 A Real-time Object Detection LSI Based on Stereo Vision for Mobile Videophone Tomohiro Arikado, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.)
(12) 15:35-16:00 C-based design of a Particle Tracking System Hirokazu Uetsu, Takahiro Ohguchi, Kenichi Jyoko, Koji Sakai, Takashi Kambe (Kinki Univ.)
(13) 16:00-16:25 A System LSI Design Environment with Java Language Manabu Koyama, Hiroyuki Terai, Kazuhiko Nakahara, Masaki Matsumoto (Kinki Univ.), Akihisa Yamada (SHARP), Takashi Kambe (Kinki Univ.)
(14) 16:25-16:50 Conversion Method from High-Level hardware Description to Equivalence Logic Formulae Kwanghoon Jung, Shinji Kimura (Waseda Univ)
Fri, Mar 10 AM 
09:15 - 10:55
(15) 09:15-09:40 Low Power Design of System LSI in the Presence of Leakage Current of MOSFET Shigeyoshi Watanabe (Shonan Inst. of Tech.)
(16) 09:40-10:05 A design platform for battery drived lowpower systems Tatsuya Koyagi, Hiroyoshi Hirai, Chihiro Mori, Masahiro Fukui (Rits)
(17) 10:05-10:30 A proposal for modeling the battery life time for battery drived systems Chihiro Mori, Tatsuya Koyagi, Masahiro Fukui (Rits)
(18) 10:30-10:55 A simulation technique of dynamic power supply / ground noise in large-scale digital LSIs Toshifumi Uemura, Makoto Nagata (Kobe Univ)
  10:55-11:05 Break ( 10 min. )
Fri, Mar 10 AM 
11:05 - 11:55
(19) 11:05-11:55 [Invited Talk]
Digital Photo Albuming using Descriptive Metadata
-- MPEG-7 Signal characteristic description tools for MPEG-A Photo Player --
Akio Yamada (NEC)
Fri, Mar 10 PM 
13:10 - 14:50
(20) 13:10-13:35 A Fault Tolerant LUT Cascade Emulator Hiroki Nakahara, Tsutomu Sasao (K.I.T)
(21) 13:35-14:00 A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Technology Teruhito Tanaka, Kouji Hatada, Tetsuya Konishi, Yoshikazu Odajima, Takashi Kambe (Kinki Univ.)
(22) 14:00-14:25 Coarse-grained Reconfigurable Hardware with Mapping Mechanisms of Floating Point Operations and Chained Additions Hidemi Akutsu, Shinji Kimura (Waseda Univ.)
(23) 14:25-14:50 A reconfigurable circuit to utilize and compensate device variations Manabu Kotani, Kazuya Katsuki, Kosuke Ogata, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
  14:50-15:10 Break ( 20 min. )
Fri, Mar 10 PM 
15:10 - 16:25
(24) 15:10-15:35 Transistor sizing for LCD driver circuit under constraint of charged pixel voltage Takahito Ijichi, Masanori Hashimoto (Osaka Univ.), Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo)
(25) 15:35-16:00 An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)
(26) 16:00-16:25 Impact of Three-Dimensional Transistor on the pattern area reduction for ULSI Shigeyoshi Watanabe (Shonan Inst. of Tech.)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yusuke Matsunaga (Kyushu University)
TEL +81-92-583-7621, FAX +81-92-583-1338
E-: ccekshu-u 
Announcement You will see the latest information at the below WEB page.
http://www.ieice.org/vld/index.html
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Yoshiharu Aimoto (NEC Electronics Corporation)
TEL +81-44-435-1258, +81-44-435-1878
E-:aicel 


Last modified: 2006-03-09 10:09:53


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