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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Noriyuki Minegishi (Mitsubishi Electric)
Vice Chair Nozomu Togawa (Waseda Univ.)
Secretary Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Koji Nakano (Hiroshima Univ.)
Vice Chair Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu)
Secretary Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.)
Assistant Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Masato Motomura (Hokkaido Univ.)
Vice Chair Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (RIKEN)
Secretary Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Koji Inoue (Kyushu Univ.)
Secretary Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Lab.), Yohei Hasegawa (Toshiba Memory)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yutaka Tamiya (Fujitsu Lab.)
Secretary Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.), Eiichi Hosoya (NTT)

Conference Date Wed, Jan 30, 2019 10:30 - 20:00
Thu, Jan 31, 2019 09:30 - 16:20
Topics FPGA Applications, etc. 
Conference Place  
Transportation Guide https://www.keio.ac.jp/en/maps/hiyoshi.html
Sponsors This conference is supported by IEEE CEDA All Japan Joint Chapter.
Participation Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Participant fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the participant fee page. We request the participant fee to participants who will attend the workshop(s) on RECONF, VLD, CPSY.

Wed, Jan 30 AM 
10:30 - 12:10
(1)
VLD
10:30-10:55 On Delay Optimization for Improving General Synchronous Performance Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
(2)
VLD
10:55-11:20 Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm Masaki Ogino, Yuki Tanaka, Shugang Wei (Gunma Univ.)
(3)
VLD
11:20-11:45 An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
(4) 11:45-12:10 (Cancelled)
  12:10-13:30 Lunch Break ( 80 min. )
Wed, Jan 30 PM 
13:30 - 14:45
(5)
RECONF
13:30-13:55 A CNN with a Noise Addition for Efficient Implementation on an FPGA Atsuki Munakata, Shimpei Satou, Hiroki Nakahara (Tokyo Tech)
(6)
RECONF
13:55-14:20 Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)
(7)
RECONF
14:20-14:45 Study of stacked full adder circuit with fabrication technology of 3D flash memory Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.)
  14:45-15:05 Break ( 20 min. )
Wed, Jan 30 PM 
15:05 - 16:20
(8)
RECONF
15:05-15:30 Design and implementation of FPGA measurement feedback system in Coherent Ising Machine Toshimori Honjo, Takahiro Inagaki, Kensuke Inaba, Takuya Ikuta, Hiroki Takesue (NTT)
(9)
RECONF
15:30-15:55 An integrated development platform of FPGA for ROS-based autonomous mobile robot Sou Tamura, Yasuhiro Nitta, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ)
(10)
RECONF
15:55-16:20 Implementation of Image Processing Algorithm Aiming for Autonomous Car Using FPGA Koki Honda, Wei Kaije, Hideharu Amano (Keio Univ.)
  16:20-16:40 Break ( 20 min. )
Wed, Jan 30 PM 
16:40 - 17:40
(11)
CPSY
16:40-17:40 [Invited Talk]
Large Scale PC Cluster Technologies
-- 20 years and future perspectives perspectives --
Kohta Nakashima (Fujitsu lab.)
  17:40-18:00 Break ( 20 min. )
Wed, Jan 30 PM 
18:00 - 20:00
  -  
Thu, Jan 31 AM 
09:30 - 10:45
(12)
CPSY
09:30-09:55 The Evaluation of Partial Reconfiguration for FiCSW Miho Yamakura, Keita Azegami, Kazusa Musha, Hideharu Amano (Keio Univ.)
(13)
CPSY
09:55-10:20 A Deduplication Mechanism for Effectively-once Semantics Using FPGA NIC Koji Suzuki, Koya Mitsuzuka, Takuma Iwata, Hiroki Matsutani (Keio Univ.)
(14)
CPSY
10:20-10:45 Preliminary Evaluation of Parallel Processing Performance on MPI Runtime Environment for Android OS Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.)
  10:45-11:00 Break ( 15 min. )
Thu, Jan 31 PM 
11:00 - 12:15
(15)
CPSY
11:00-11:25 A Case for Unsupervised Abnormal Behavior Detection Using Multiple Online Sequential Learning Cores Rei Ito, Mineto Tsukada (Keio Univ), Masaaki Kondo (Univ Tokyo), Hiroki Matsutani (Keio Univ)
(16)
CPSY
11:25-11:50 Area and Performance Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
(17) 11:50-12:15  
  12:15-13:35 Lunch Break ( 80 min. )
Thu, Jan 31 PM 
13:35 - 14:50
(18)
RECONF
13:35-14:00
(19)
RECONF
14:00-14:25 Preliminary evaluation of special instruction implementation methods by high level synthesis Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT)
(20)
RECONF
14:25-14:50
  14:50-15:05 Break ( 15 min. )
Thu, Jan 31 PM 
15:05 - 16:20
(21)
RECONF
15:05-15:30
(22)
RECONF
15:30-15:55 Takefumi Miyoshi (TOYOTA ITC)
(23)
RECONF
15:55-16:20 An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Koyo Nitta (NTT)
E-: t 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-:

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/ 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Masato Motomura(Hokkaido Univ.)
E-: isti 
Announcement http://www.ieice.org/~reconf/
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Yukio Mitsuyama (Kochi Univ. of Tech.)
E-:o- 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2019-01-30 10:56:56


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