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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Atsushi Takahashi (Osaka Univ.)
Vice Chair Akira Onozawa (NTT)
Secretary Nozomu Togawa (Waseda Univ.), Akihisa Yamada (Sharp)

Conference Date Wed, Mar 10, 2010 13:30 - 17:55
Thu, Mar 11, 2010 10:00 - 17:20
Fri, Mar 12, 2010 10:00 - 15:50
Topics Design Technology for System-on-Silicon 
Conference Place  
Address 3-11-1 Nishi, Naha-shi, Okinawa, Japan
Transportation Guide http://www.tiruru.or.jp/?page_id=31
Contact
Person
Prof. Katsuhiko Shimabukuro
+81-98-895-8694

Wed, Mar 10 PM 
13:30 - 14:45
(1) 13:30-13:55 An Automatic Layout System for Timing Pulse Generator of Small LCD Driver Circuits Shohei Asakawa, Yuichi Sakakibara, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo), Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota (Sharp Corp.)
(2) 13:55-14:20 Analog Macro Layout Generation Based on Regular Bulk Structure Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
(3) 14:20-14:45 Circuit Structure of Level Shifter for Sub-threshold Operation Tomohiro Ishizaki, Satoshi Koyama, Kimiyoshi Usami (Shibaura Int. of Tech.)
  14:45-15:00 Break ( 15 min. )
Wed, Mar 10 PM 
15:00 - 16:40
(4) 15:00-15:25 A Delay Variation Modeling Algorithm with Considering Supply Voltage and Local Temperature Hideki Yanagawa, Haruo Miki, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
(5) 15:25-15:50 Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST)
(6) 15:50-16:15 Variation-Tolerant Decomposition of MOS Transistor Bo Liu, Atsushi Ochi, Shigetoshi Nakatake (Univ. of Kitakyushu)
(7) 16:15-16:40 An efficient technique to search failure-areas for yield estimation via partial hyperspherephere Takanori Date, Shiho Hagiwara, Kazuya Masu (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.)
  16:40-16:55 Break ( 15 min. )
Wed, Mar 10 PM 
16:55 - 17:55
(8) 16:55-17:55 [Invited Talk]
Changing Organization through Continuous Data Collection with Business Microscope
Koji Ara, Nobuo Sato, Kazuo Yano (Hitachi), Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda)
Thu, Mar 11 AM 
10:00 - 11:40
(9) 10:00-10:25 Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block Shouta Yamada, Yuuichi Kokushou, Tomohiro Nishimoto, Naoyuki Yoshida, Ryohei Hori, Naoki Matsumoto, Tatsuya Kitamori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(10) 10:25-10:50 Examination of the best basic logic gate architecture for Via programmable logic device Ryohei Hori, Yuuichi Kokushou, Tomohiro Nishimoto, Shouta Yamada, Naoyuki Yoshida, Naoki Matsumoto, Takeshi Fujino (Ritsumei Univ.), Masaya Yoshikawa (Meijo Univ.)
(11) 10:50-11:15 Wiring delay of Logic Element used in Via programmable logic device VPEX Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ)
(12) 11:15-11:40 High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
  11:40-13:05 Lunch ( 85 min. )
Thu, Mar 11 PM 
13:05 - 14:20
(13) 13:05-13:30 On an Accuracy Improvement of a Statistical Timing Analysis Using Gaussian Mixture Models Atsutaka Obata, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.)
(14) 13:30-13:55 Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.)
(15) 13:55-14:20 Implementation Scheme for Power Gating and its Influence to Energy Reduction Yuya Ohta, Satoshi Koyama, Tatsunori Hashida, Tetsuya Muto, Tatsuya Yamamoto, Kimiyoshi Usami (Shibaura Institute of Tech.)
  14:20-14:35 Break ( 15 min. )
Thu, Mar 11 PM 
14:35 - 15:50
(16) 14:35-15:00 A Break Even Time Prediction of Run-Time Power Gating Circuits by an On-chip Leakage Monitor using an MTCMOS circuit Satoshi Koyama, Tatsunori Hashida, Kimiyoshi Usami (Shibaura Inst. of Tech.), Daisuke Ikebuchi, Hideharu Amano (Keio Univ.)
(17) 15:00-15:25 Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.)
(18) 15:25-15:50 Analytical Evaluation of Average Switching Energy of Adders Shinji Ohno, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
  15:50-16:05 Break ( 15 min. )
Thu, Mar 11 PM 
16:05 - 17:20
(19) 16:05-16:30 Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages Masaki Kinoshita (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agr and Tech.), Atsushi Takahashi (Osaka Univ.)
(20) 16:30-16:55 Clock Distribution Optimization under Deskew Mitsuhiro Yamaguchi, Yasuhiro Takashima (Univ. of Kitakyushu)
(21) 16:55-17:20 Clustering Method for Low Power Clock Tree in General Syncrhonous Framework Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Osaka univ)
Fri, Mar 12 AM 
10:00 - 11:40
(22) 10:00-10:25 Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors Takahiro Kumura (NEC/Osaka Univ.), Soichiro Taga, Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
(23) 10:25-10:50 Performance evaluation of ADDER with Error-Detection-Correction Mechanism Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ)
(24) 10:50-11:15 High-Level Design Conditions for Post-Fabrication Timing-Adjustable Datapaths Akira Tehara, Mineo Kaneko (JAIST)
(25) 11:15-11:40 A Comparison of Two Approximate String Matching Algorithms Implemented on an FPGA Keisuke Shimizu, Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
  11:40-13:05 Lunch ( 85 min. )
Fri, Mar 12 PM 
13:05 - 14:20
(26) 13:05-13:30 Estimating Signal Transition Frequency of Arithmetic Circuits Using Cell Delay Model Hirotaka Kawashima, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
(27) 13:30-13:55 Circuit conversion for reducing false negatives on formal verification of sequential circuit Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
(28) 13:55-14:20 An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
  14:20-14:35 Break ( 15 min. )
Fri, Mar 12 PM 
14:35 - 15:50
(29) 14:35-15:00 Design and Implementation of an AMBA AHB Compliant Bus Architecture on FPGA Xuan-Tu Tran, Hai-Phong Phan, Van-Huan Tran, Quang-Vinh Tran, Ngoc-Binh Nguyen (Vietnam National Univ.)
(30) 15:00-15:25 An ASIC implementation of a group signature algorithm using two-level behavioral synthesis Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC)
(31) 15:25-15:50 A Design of an Adaptive Network on Chip for the Many-core System Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Nozomu Togawa (Waseda Univ.)
E-: n
Tel: +81-3-5286-3908, Fax: +81-3-3208-7439 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/


Last modified: 2010-03-02 22:03:09


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