IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Daisuke Fukuda (Fujitsu Labs.)
Vice Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Makoto Nagata (Kobe Univ.)
Vice Chair Masafumi Takahashi (
Secretary Masatoshi Tsuge (Socionext), Tetsuya Hirose (Osaka Univ.)
Assistant Koji Nii (TSMC), Kosuke Miyaji (Shinshu Univ.), Takeshi Kuboki (Kyushu Univ.)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Hiroshi Takahashi (Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)
Assistant Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yuichi Nakamura (NEC)
Secretary Kenshu Seto (Tokyo City Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Kazuki Oya (Mitsubishi Electric), Masayuki Hiromoto (Fujistu Lab.)

Conference Date Tue, Nov 17, 2020 09:30 - 15:40
Wed, Nov 18, 2020 09:30 - 15:15
Topics Design Gaia 2020 -New Field of VLSI Design- 
Conference Place  
Sponsors This conference is co-sponsored by IEEE CEDA All Japan Joint Chapter; IEEE CASS Japan Joint Chapter .
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, DC, RECONF, ICD.

Tue, Nov 17 AM 
09:30 - 10:20
09:30-09:55 Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation VLD2020-11 ICD2020-31 DC2020-31 RECONF2020-30 Takaki Urabe, Koji Nii, Kazutoshi Kobayashi (KIT)
09:55-10:20 A Study on Power Gating Switch Control Technique for Nonvolatile Logic LSI VLD2020-12 ICD2020-32 DC2020-32 RECONF2020-31 Fangcen Zhong, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)
Tue, Nov 17 AM 
10:30 - 11:45
10:30-10:55 Power Analysis Based on Probability Calculation of Small Regions in LSI VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
10:55-11:20 DET Flip-Flops with SEU Detection Capability Using DICE and C-Element VLD2020-14 ICD2020-34 DC2020-34 RECONF2020-33 Xu Haijia, Kazuteru Namba (Chiba Univ.)
11:20-11:45 Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test VLD2020-15 ICD2020-35 DC2020-35 RECONF2020-34 Hikaru Tamaki, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas)
  11:45-13:00 Lunch Break ( 75 min. )
Tue, Nov 17 PM 
13:00 - 14:00
13:00-14:00 [Keynote Address]
Prospect of Large-Scale Neural-Network Simulation by Exa-scale Computing
Jun Igarashi (RIKEN)
Tue, Nov 17 PM 
14:00 - 15:15
14:00-14:25 VLD2020-16 ICD2020-36 DC2020-36 RECONF2020-35
14:25-14:50 Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder VLD2020-17 ICD2020-37 DC2020-37 RECONF2020-36 Naoto Soga, Shimpei Sato, HIroki Nakahara (Tokyo Tech)
14:50-15:15 VLD2020-18 ICD2020-38 DC2020-38 RECONF2020-37
Tue, Nov 17 AM 
09:30 - 11:10
09:30-09:55 Analysis of Resistance Distribution in Chips with Inductive Coupling Wireless Communication Interface VLD2020-19 ICD2020-39 DC2020-39 RECONF2020-38 Hideto Kayashima, Hideharu Amano, Tsunaaki Shidei (Keio Univ.)
09:55-10:20 Efficient computation of inductive invariant through flipflop selection VLD2020-20 ICD2020-40 DC2020-40 RECONF2020-39 Fudong Wang, Masahiro Fujita (U-Tokyo)
10:20-10:45 R-GCN Based Function Inference for An Arithmetic Circuit VLD2020-21 ICD2020-41 DC2020-41 RECONF2020-40 Yuichiro Fujishiro, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.), Hiroto Ito, Daisuke Ido (MITSUBISHI ELECTRIC ENGINEERING)
10:45-11:10 Implementation of YOLO in the AI accelerator ReNA VLD2020-22 ICD2020-42 DC2020-42 RECONF2020-41 Toma Uemura, Yasuhiro Nakahara, Motoki Amagasaki, Masato Kiyama, Masahiro Iida (Kumamoto Univ.)
  11:10-14:00 Lunch Break ( 170 min. )
Tue, Nov 17 PM 
14:00 - 15:40
14:00-14:25 Quantum Circuit Design by Steiner-Gauss with Considering the Order of Qubits VLD2020-23 ICD2020-43 DC2020-43 RECONF2020-42 Zhengtong Han, Shigeru Yamashita (Ritsumei Univ.)
14:25-14:50 Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 Ryosuke Matsuo, Shin-ichi Minato (Kyoto Univ)
14:50-15:15 Restricted-Area and Fast Sample Preparation of a Fluid using Programmable Microfluidic Devices VLD2020-25 ICD2020-45 DC2020-45 RECONF2020-44 Ou Suiketsu, Yamashita Shigeru (Ritsumei Univ.), Sudip Roy (Indian Institute of Technology (IIT) Roorkee), Juinn-Dar Huang (National Chiao Tung University)
15:15-15:40 Transformation of Mixing Graphs Considering Splitting Errors on Digital Microfluidic Biochip VLD2020-26 ICD2020-46 DC2020-46 RECONF2020-45 Ikuru Yoshida, Shigeru Yamashita (Ritsumeikan Univ.)
Wed, Nov 18 AM 
09:30 - 10:45
09:30-09:55 Study on Design Guidelines for Low Power Capsule Endoscope System Using Compressed Sensing VLD2020-27 ICD2020-47 DC2020-47 RECONF2020-46 Yuuki Harada, Daisuke Kanemoto (Osaka Univ.), Makoto Ohki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.)
09:55-10:20 Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor VLD2020-28 ICD2020-48 DC2020-48 RECONF2020-47 Takashi Kojima (TUS), Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS)
10:20-10:45 VLD2020-29 ICD2020-49 DC2020-49 RECONF2020-48
  10:45-13:35 Lunch Break ( 170 min. )
Wed, Nov 18 PM 
14:00 - 15:15
14:00-14:25 Measurement Results of Total Ionizing Dose Effect on Ring Oscillators Fabricated by a Thin-BOX FDSOI Process for Outer-space Mission VLD2020-30 ICD2020-50 DC2020-50 RECONF2020-49 Takashi Yoshida, Jun Furuta, Kazutoshi Kobayashi (KIT)
14:25-14:50 On-chip power supply noise monitoring for evaluation of multi-chip board power delivery networks VLD2020-31 ICD2020-51 DC2020-51 RECONF2020-50 Daichi Nakagawa, Kazuki Yasuda, Masaru Mashiba, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univ)
14:50-15:15 Evaluation of operating performance of ECDSA hardware module II VLD2020-32 ICD2020-52 DC2020-52 RECONF2020-51 Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
Wed, Nov 18 AM 
09:30 - 10:45
09:30-09:55 Comparing RISC-V RV32I and MIPS R3000 as a model processor for education VLD2020-33 ICD2020-53 DC2020-53 RECONF2020-52 Hideharu Amano, Kensuke Iizuka, Kohei Itoh (Keio Univ.)
09:55-10:20 Seat Layout Method Considering Physical Distance Using Cell Placement Methods in LSI VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53 Yukihide Kohira (Univ. of Aizu)
10:20-10:45 N/A VLD2020-35 ICD2020-55 DC2020-55 RECONF2020-54 Tomoya Wakaizumi, Kazunari Takasaki, Yuta Yachi, Tomokazu Yoshimura, Makoto Nishizawa, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
Wed, Nov 18 AM 
11:00 - 11:50
(27) 11:00-11:25  
(28) 11:25-11:50  
  11:50-13:00 Lunch Break ( 70 min. )
Wed, Nov 18 PM 
13:00 - 14:00
13:00-14:00 [Keynote Address]
Quality Assurances of the Fugaku Supercomputer: Function, Performance and Power VLD2020-36 ICD2020-56 DC2020-56 RECONF2020-55
Takahide Yoshikawa (FLAB)
Wed, Nov 18 PM 
14:00 - 14:50
14:00-14:25 Physically Unclonable Functions(PUF) curcuit using Non-Volatile Flip-Flop and security evaluation against modeling attacks VLD2020-37 ICD2020-57 DC2020-57 RECONF2020-56 Hiroki Ishihara, Kimiyoshi Usami (Shibaura IT)
14:25-14:50 Energy Efficient Approximate Storing of Image Data for Non-volatile Memory VLD2020-38 ICD2020-58 DC2020-58 RECONF2020-57 Yoshinori Ono, Kimiyoshi Usami (SIT)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address  
Announcement See also VLD's homepage:
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address  
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address  
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kenshu Seto (Tokyo City University)
E-: ktcu 
Announcement Please see the IPSJ-SLDM page below:

Last modified: 2020-11-16 11:16:57

Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.

[On-Site Price List of Paper Version of Proceedings (Technical Report)] (in Japanese)
[Presentation and Participation FAQ] (in Japanese)
[Cover and Index of IEICE Technical Report by Issue]

[Return to VLD Schedule Page]   /   [Return to ICD Schedule Page]   /   [Return to DC Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan