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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Vice Chair Noriyuki Minegishi (Mitsubishi Electric)
Secretary Shinobu Nagayama (Hiroshima City Univ.), Koyo Nitta (NTT)

Technical Committee on Component Parts and Materials (CPM) [schedule] [select]
Chair Fumihiko Hirose (Yamagata Univ.)
Vice Chair Mayumi Takeyama (Kitami Inst. of Tech.)
Secretary Nobuyuki Iwata (Nihon Univ.), Yuichi Nakamura (Toyohashi Univ. of Tech.)
Assistant Yuichi Akage (NTT)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Hideto Hidaka (Renesas)
Vice Chair Makoto Nagata (Kobe Univ.)
Secretary Makoto Takamiya (Univ. of Tokyo), Takashi Hashimoto (Panasonic)
Assistant Masanori Natsui (Tohoku Univ.), Masatoshi Tsuge (Socionext), Hiroyuki Ito (Tokyo Inst. of Tech.), Pham Konkuha (Univ. of Electro-Comm.)

Technical Committee on Image Engineering (IE) [schedule] [select]
Chair Takayuki Hamamoto (Tokyo Univ. of Science)
Vice Chair Kazuya Kodama (NII), Hideaki Kimata (NTT)
Secretary Keita Takahashi (Nagoya Univ.), Kei Kawamura (KDDI Research)
Assistant Yasutaka Matsuo (NHK), Kazuya Hayase (NTT)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Koji Nakano (Hiroshima Univ.)
Vice Chair Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu)
Secretary Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.)
Assistant Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Michiko Inoue (NAIST)
Vice Chair Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Secretary Masayoshi Yoshimura (Kyoto Sangyo Univ.), Haruhiko Kaneko (Tokyo Inst. of Tech.)
Assistant Masayuki Arai (Nihon Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Masato Motomura (Hokkaido Univ.)
Vice Chair Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (Tohoku Univ.)
Secretary Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Special Interest Group on System Architecture (IPSJ-ARC) [schedule] [select]
Chair Masahiro Goshima (NII)
Secretary Takatsugu Ono (Kyushu Univ.), Masaaki Kondo (Univ. of Tokyo), Yohei Hasegawa (Toshiba), Ryota Shioya (Nagoya Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Kiyoharu Hamaguchi (Shimane Univ.)
Secretary Ko Kyo (Panasonic), Yukio Mitsuyama (Kochi Univ. of Tech.), Seiya Shibata (NEC)

Special Interest Group on Embedded Systems (IPSJ-EMB) [schedule] [select]

{INFOMESITEM}
Conference Date Mon, Nov 6, 2017 10:30 - 17:30
Tue, Nov 7, 2017 09:00 - 20:30
Wed, Nov 8, 2017 09:00 - 16:45
Topics Design Gaia 2017 -New Field of VLSI Design- 
Conference Place  
Sponsors This conference is supported by IEEE CEDA All Japan Joint Chapter and IEEE CAS Society Fukuoka Chapter.
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Mon, Nov 6 AM 
10:30 - 11:45
(1)
VLD
10:30-10:55 hCODE 2.0: An Open-source Platform for FPGA Cluster System VLD2017-27 DC2017-33 Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(2)
VLD
10:55-11:20 Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis VLD2017-28 DC2017-34 Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.)
(3)
VLD
11:20-11:45 Considerations of Inside Structures for Approximate Multipliers VLD2017-29 DC2017-35 Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
  11:45-13:00 Lunch Break ( 75 min. )
Mon, Nov 6 PM 
13:00 - 13:45
(4)
ICD
13:00-13:45 [Invited Talk]
Superconducting quantum computing CPM2017-79 ICD2017-38 IE2017-64
Yasunobu Nakamura (UTokyo)
Mon, Nov 6 PM 
13:00 - 14:15
(5)
VLD
13:00-13:25 Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves VLD2017-30 DC2017-36 Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.)
(6)
VLD
13:25-13:50 Hardware Implementation of Elliptic Curve Cryptography for Sensor-Node Applications Ryosuke Saito, Hiromitsu Awano, Makoto Ikeda (The Univ. of Tokyo)
(7)
DC
13:50-14:15 An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores VLD2017-31 DC2017-37 Hashidate Hidemi, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (Kyoto Sangyo Univ.)
Mon, Nov 6 PM 
13:00 - 14:15
(8)
RECONF
13:00-13:25 FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving RECONF2017-37 Masahiro Fukuda, Yasushi Inoguchi (JAIST)
(9)
RECONF
13:25-13:50 RECONF2017-38
(10)
RECONF
13:50-14:15 RECONF2017-39 Ryo Kamasaka, Taisei Segawa, Yuichiro Shibata (Nagasaki Univ.)
  14:15-14:30 Break ( 15 min. )
Mon, Nov 6 PM 
14:30 - 15:45
(11)
VLD
14:30-14:55 Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure VLD2017-32 DC2017-38 Yasuhiro Ogasahara, Toshihiro Sekigawa, Hanpei Koike (AIST)
(12)
VLD
14:55-15:20 Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control VLD2017-33 DC2017-39 Yusuke Yoshida, Kimiyoshi Usami (SIT)
(13)
VLD
15:20-15:45 A shared memory chip for twin-tower of chips VLD2017-34 DC2017-40 Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.)
Mon, Nov 6 PM 
14:30 - 15:45
(14)
DC
14:30-14:55 A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST VLD2017-35 DC2017-41 Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.)
(15)
DC
14:55-15:20 An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction VLD2017-36 DC2017-42 Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics)
(16)
DC
15:20-15:45 A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation VLD2017-37 DC2017-43 Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
  15:45-16:00 Break ( 15 min. )
Mon, Nov 6 PM 
16:00 - 17:30
  -  
Tue, Nov 7 AM 
09:00 - 10:15
(17)
VLD
09:00-09:25 Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch VLD2017-38 DC2017-44 Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(18)
VLD
09:25-09:50 Routing method considering programming constraint of reconfigurable device using via-switch crossbars VLD2017-39 DC2017-45 Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(19)
VLD
09:50-10:15 A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit VLD2017-40 DC2017-46 Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
Tue, Nov 7 AM 
09:00 - 10:15
(20)
DC
09:00-09:25 Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST VLD2017-41 DC2017-47 Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech)
(21)
DC
09:25-09:50 On Avoiding Test Data Corruption by Optimal Scan Chain Grouping VLD2017-42 DC2017-48 Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD)
(22)
VLD
09:50-10:15 On low power oriented test pattern compaction using SAT solver VLD2017-43 DC2017-49 Yusuke Matsunaga (Kyushu Univ.)
Tue, Nov 7 AM 
09:00 - 10:15
(23)
RECONF
09:00-09:25 Real Chip Evaluation of a Variable Pipelined Coarse-Grained Reconfigurable Array RECONF2017-40 Naoki Ando, Takuya Kojima, Hideharu Amano (Keio Univ.)
(24)
RECONF
09:25-09:50 RECONF2017-41
(25)
RECONF
09:50-10:15 Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking RECONF2017-42 Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
  10:15-10:30 Break ( 15 min. )
Tue, Nov 7 AM 
10:30 - 11:45
(26)
VLD
10:30-10:55 Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table VLD2017-44 DC2017-50 Yuji Shindo, Kenshu Seto, Hao San (TCU)
(27)
VLD
10:55-11:20 A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication VLD2017-45 DC2017-51 Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.)
(28)
VLD
11:20-11:45 Implementation and Optimization of Parallel Prefix Adder Using Majority Function VLD2017-46 DC2017-52 Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
Tue, Nov 7 AM 
10:30 - 11:45
(29)
VLD
10:30-10:55 Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits VLD2017-47 DC2017-53 Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
(30)
VLD
10:55-11:20 Stochastic logic circuit using static constant as coefficient without random number generator VLD2017-48 DC2017-54 Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(31)
DC
11:20-11:45 Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time VLD2017-49 DC2017-55 Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
Tue, Nov 7 AM 
10:30 - 11:45
(32)
RECONF
10:30-10:55 RECONF2017-43
(33)
RECONF
10:55-11:20 RECONF2017-44
(34)
RECONF
11:20-11:45 IoT Platform using an MCU-FPGA Hybrid System and Feasibility Study of Wireless Configuration RECONF2017-45 Ryota Suzuki, Hironori Nakajo (TUAT)
  11:45-13:00 Lunch Break ( 75 min. )
Tue, Nov 7 PM 
13:00 - 13:45
(35)
VLD
13:00-13:45 [Invited Talk]
Innovative Applications of Machine Learning in Lithography and DFM VLD2017-50 DC2017-56
Tetsuaki Matsunawa (Toshiba Memory)
Tue, Nov 7 PM 
13:00 - 14:15
(36)
ICD
13:00-13:25 A Low-Voltage Operation Self-Calibration Hysteresis Comparator CPM2017-80 ICD2017-39 IE2017-65 Takumi Saito, Satoshi Komatsu (TDU)
(37)
ICD
13:25-13:50 Real chip evaluation of a low-power overhead body bias controller CPM2017-81 ICD2017-40 IE2017-66 Hayate Okuhara, Akram BenAhmed, Hideharu Amano (Keio Univ.)
(38)
ICD
13:50-14:15 Low Voltage Operation Boost Converter for ReRAM/NAND Flash Memory Hybrid SSD CPM2017-82 ICD2017-41 IE2017-67 Kenta Suzuki, Kota Tsurumi, Ken Takeuchi (Chuo Univ.)
Tue, Nov 7 PM 
13:00 - 14:15
(39)
RECONF
13:00-13:25 Calculation method of exponential function on FPGAs using high-radix STL method RECONF2017-46 Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
(40)
RECONF
13:25-13:50 RECONF2017-47
(41)
RECONF
13:50-14:15 RECONF2017-48
  14:15-14:30 Break ( 15 min. )
Tue, Nov 7 PM 
14:00 - 15:15
(42)
VLD
14:00-14:25 * VLD2017-51 DC2017-57 Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(43)
VLD
14:25-14:50 * VLD2017-52 DC2017-58 Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(44)
DC
14:50-15:15 A Detection Method for Trojan Circuit inserted in Manufacturing Process VLD2017-53 DC2017-59 Yoshinobu Okuda, Masayoshi Yoshimura, Kohei Ohyama (Kyoto Sangyo Univ.)
Tue, Nov 7 PM 
14:30 - 15:45
(45)
ICD
14:30-14:55 Design of Weak-Signal-Readout-System for Terahertz-Video-Imaging CPM2017-83 ICD2017-42 IE2017-68 Toshiyuki Kikkawa, Makoto Ikeda (The Univ. of Tokyo)
(46)
ICD
14:55-15:20 Simulation Techniques for EMC Compliant Design of Automotive IC Chips and Modules CPM2017-84 ICD2017-43 IE2017-69 Akihiro Tsukioka, Makoto Nagata, Kohki Taniguchi, Daisuke Fujimoto (Kobe Univ.), Rieko Akimoto, Takao Egami, Kenji Niinomi, Takeshi Yuhara, Sachio Hayashi (TOSHIBA), Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang (ANSYS)
(47)
ICD
15:20-15:45 Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature CPM2017-85 ICD2017-44 IE2017-70 Kentaro Kato, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)
Tue, Nov 7 PM 
14:30 - 15:45
(48)
CPSY
14:30-14:55 CPSY2017-40
(49)
CPSY
14:55-15:20 DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits CPSY2017-41 Shin-ichi O'uchi, Hiroshi Fuketa, Ryousei Takano (AIST)
(50) 15:20-15:45  
  15:45-16:00 Break ( 15 min. )
Tue, Nov 7 PM 
15:30 - 16:45
(51) 15:30-15:55  
(52) 15:55-16:20  
(53) 16:20-16:45  
Tue, Nov 7 PM 
16:00 - 16:45
(54)
ICD
16:00-16:45 [Invited Talk]
Researchs on high-speed and efficient Deep Learning technologies CPM2017-86 ICD2017-45 IE2017-71
Takuya Fukagai, Koichi Shirahata, Yasumoto Tomita, Tetsutaro Hashimoto, Atsushi Ike, Masafumi Yamazaki, Akihiko Kasagi, Tsuguchika Tabaru (Fujitsu Lab. Ltd.), Liuan Wang, Song Wang, Li Sun, Jun Sun (FRDC)
Tue, Nov 7 PM 
16:00 - 16:45
(55)
CPSY
16:00-16:45 [Invited Talk]
Application of Real-time Image Recognition System with Machine and Transfer Learnings to Computer-Aided Diagnosis for Endoscopic Images of Colorectal Cancer CPSY2017-42
Tetsushi Koide, Toru Tamaki (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Medical Corp. JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ. Hospital)
  16:45-17:00 Break ( 15 min. )
Tue, Nov 7 PM 
17:00 - 17:50
(56) 17:00-17:50 [Keynote Address]
Theory and applications of dynamical sparse modeling VLD2017-54 CPM2017-87 ICD2017-46 IE2017-72 CPSY2017-43 DC2017-60 RECONF2017-49
Masaaki Nagahara (Univ. of Kitakyushu)
Tue, Nov 7 PM 
18:30 - 20:30
  -  
Wed, Nov 8 AM 
09:00 - 10:15
(57)
CPSY
09:00-09:25 CPSY2017-44
(58) 09:25-09:50  
(59) 09:50-10:15  
Wed, Nov 8 AM 
09:00 - 10:15
(60)
VLD
09:00-09:25 A Packet Lookup Engine LSI with Automatic Rule Registration and Deletion Function VLD2017-55 DC2017-61 Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.)
(61)
VLD
09:25-09:50 Real-time coefficient optimization method for PAM-4 transmitter equalizer VLD2017-56 DC2017-62 Yosuke Iijima, Keigo Taya (NIT, Oyama college), Yasushi Yuminaka (Gunma Univ.)
(62)
VLD
09:50-10:15 A General Model of Timing Correction by Temperature Dependent Clock Skew VLD2017-57 DC2017-63 Mineo Kaneko (JAIST)
  10:15-10:30 Break ( 15 min. )
Wed, Nov 8 AM 
10:30 - 11:30
(63) 10:30-11:30  
  11:30-12:30 Lunch Break ( 60 min. )
Wed, Nov 8 PM 
12:30 - 13:45
(64) 12:30-12:55  
(65)
CPSY
12:55-13:20 CPSY2017-45
(66)
CPSY
13:20-13:45 Analysis of Data Access Locality from Redis KVS Database CPSY2017-46 Hiroyuki Baba, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
Wed, Nov 8 PM 
12:45 - 13:45
(67)
IE
12:45-13:45 [Invited Talk]
Accurate Color Reproduction using Multiband Image and Its Applications CPM2017-88 ICD2017-47 IE2017-73
Masaru Tsuchida, Kaoru Hiramatsu, Kunio Kashino (NTT)
Wed, Nov 8 PM 
12:30 - 13:45
(68)
DC
12:30-12:55 Application of blind watermarking method for secondary use on smart community VLD2017-58 DC2017-64 Yuta Ohno, Akira Niwa, Hiroaki Nishi (Keio Univ.)
(69) 12:55-13:20  
(70) 13:20-13:45  
  13:45-14:00 Break ( 15 min. )
Wed, Nov 8 PM 
14:00 - 15:15
(71)
CPSY
14:00-14:25 Accelerating Blockchain Search using GPU CPSY2017-47 Shin Morishima, Hiroki Matsutani (Keio Univ.)
(72)
CPSY
14:25-14:50 CPSY2017-48
(73)
CPSY
14:50-15:15 CPSY2017-49
Wed, Nov 8 PM 
14:00 - 15:15
(74)
IE
14:00-14:25 CPM2017-89 ICD2017-48 IE2017-74
(75)
IE
14:25-14:50 Pixel-Wise Exposure Controllable Column Parallel Readout Image Sensor and HDR Image Reconstruction CPM2017-90 ICD2017-49 IE2017-75 Takuro Kosaka, Takayuki Hamamoto (TUS)
(76)
IE
14:50-15:15 Global Shutter CMOS Image Sensor with Correlated Multiple Sampling Architecture CPM2017-91 ICD2017-50 IE2017-76 Hiroyuki Yamaguchi, Toshinori Otaka, Yotaro Imai, Takayuki Hamamoto (TUS)
Wed, Nov 8 PM 
14:00 - 15:15
(77) 14:00-14:25  
(78) 14:25-14:50  
(79) 14:50-15:15  
  15:15-15:30 Break ( 15 min. )
Wed, Nov 8 PM 
15:30 - 16:45
(80) 15:30-15:55  
(81) 15:55-16:45  
Wed, Nov 8 PM 
15:30 - 16:45
(82)
VLD
15:30-15:55 A Study on Target Pin-Pairs Selection for Set-Pair Routing VLD2017-59 DC2017-65 Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.)
(83)
VLD
15:55-16:20 Max Length and Length Difference Minimization for Set Pair Routing Problem with ILP VLD2017-60 DC2017-66 Shutaro Hara, Kunihiro Fujiyoshi (TUAT)
(84)
VLD
16:20-16:45 An Efficient Search Method on Stacked Rectangular Dissections VLD2017-61 DC2017-67 Masaki Yokota, Kunihiro Fujiyoshi (TUAT)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Shinobu Nagayama (Hiroshima City University)
E-: s_-cu 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPM Technical Committee on Component Parts and Materials (CPM)   [Latest Schedule]
Contact Address  
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Masanori Natsui (Tohoku Univ.)
TEL 022-217-5552,FAX 022-217-5508
E-:iec
Takashi Hashimoto (Panasonic)
TEL 06-6905-4015
E-:1967pac 
IE Technical Committee on Image Engineering (IE)   [Latest Schedule]
Contact Address Kei Kawamura (KDDI Research)
E-: ie-n2017 
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-:

CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/ 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address  
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Masato Motomura(Hokkaido Univ.)
E-: isti 
IPSJ-ARC Special Interest Group on System Architecture (IPSJ-ARC)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Yukio Mitsuyama (Kochi Univ. of Tech.)
E-:o- 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/
IPSJ-EMB Special Interest Group on Embedded Systems (IPSJ-EMB)   [Latest Schedule]
Contact Address  


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