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Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Vice Chair Hiroshi Takahashi (Ehime Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Conference Date Wed, Feb 26, 2020 10:00 - 17:00
Topics  
Conference Place  
Participation Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Participant fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the participant fee page. We request the participant fee to participants who will attend the workshop(s) on DC.

Wed, Feb 26 AM 
10:00 - 11:35
(1) 10:00-10:25 On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor Masayuki Gondo, Yousuke Miyake, Seiji Kajihara (Kyutech)
(2) 10:25-10:50 Defective Chip Prediction Modeling Using Convolutional Neural Networks Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas)
[updated]
(3) 10:50-11:15 A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
  11:15-11:35 Break ( 20 min. )
Wed, Feb 26 PM 
11:35 - 14:10
(4) 11:35-12:00 Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas)
(5) 12:00-12:25 A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
[updated]
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
(6) 12:25-12:50 Glitch PUF utilizing Unrolled Architecture and its Evaluation Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
  12:50-14:10 Break ( 80 min. )
Wed, Feb 26 PM 
14:10 - 15:45
(7) 14:10-14:35 A Don’t Care Identification-Filling Co-Optimization Method for Low Power Testing Using Partial Max-SAT
[updated]
Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ), Masayuki Arai (Nihon Univ)
(8) 14:35-15:00 Power Analysis for Logic Area of LSI Including Memory Area Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech)
(9) 15:00-15:25 Improving Controllability of Signal Transitions in the High Switching Area of LSI Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
  15:25-15:45 Break ( 20 min. )
Wed, Feb 26 PM  三宅 庸資(九工大)
15:45 - 17:00
(10) 15:45-16:10 Frequency Variation of Ring Oscillators During Long-Time Operation on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.)
(11) 16:10-16:35 Accurate Recycled FPGA Detection Based on Exhaustive Path Analysis
[updated]
Michihiro Shintani, Foisal Ahmed, Michiko Inoue (NAIST)
(12) 16:35-17:00 Soft Error Tolerance of Power-Supply-Noise Hardened Latches Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E-: ain-u 


Last modified: 2019-12-27 14:29:00


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