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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Takashi Takenana (NEC)
Vice Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary Daisuke Fukuda (Fujitsu Labs.), Shinobu Nagayama (Hiroshima City Univ.)
Assistant Parizy Matthieu (Fujitsu Labs.)

Conference Date Wed, Mar 1, 2017 14:00 - 16:45
Thu, Mar 2, 2017 09:00 - 16:40
Fri, Mar 3, 2017 09:00 - 14:15
Conference Place  
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, Mar 1 PM 
14:00 - 15:15
(1) 14:00-14:25 Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines VLD2016-102 Shota Enokido, Kimiyoshi Usami (SIT)
(2) 14:25-14:50 A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating VLD2016-103 Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
(3) 14:50-15:15 Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement VLD2016-104 Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
  15:15-15:30 Break ( 15 min. )
Wed, Mar 1 PM 
15:30 - 16:45
(4) 15:30-15:55 High accuracy 8*8 approximate multiplier based on OR operation VLD2016-105 Yi Guo, Heming Sun, Canran Jin, Shinji Kimura (Waseda Univ.)
(5) 15:55-16:20 A Design Technique for Approximate Circuits based on Artificial Neural Network VLD2016-106 Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(6) 16:20-16:45 Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models VLD2016-107 Shogo Senba, Hiroshi Saito (UoA)
Thu, Mar 2 AM 
09:00 - 10:15
(7) 09:00-09:25 Generation of Optimum Screening Patterns for a Screening Circuit to Detect Network Intrusion VLD2016-108 Tomoaki Hashimoto, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(8) 09:25-09:50 FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration VLD2016-109 Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.)
(9) 09:50-10:15 Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM VLD2016-110 Takaaki Yokoyama, Ochi Hiroyuki (Ritsumeikan Univ)
  10:15-10:30 Break ( 15 min. )
Thu, Mar 2 PM 
10:30 - 12:10
(10) 10:30-10:55 High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering VLD2016-111 Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
(11) 10:55-11:20 Acceleration of a Hotspot Detection Method Based on Approximate String Matching for LSI Mask Pattern Using Table Reference VLD2016-112 Shuma Tamagawa, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hirohima City Univ.)
(12) 11:20-11:45 Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning VLD2016-113 Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
(13) 11:45-12:10 Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing VLD2016-114 Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
  12:10-13:30 Lunch Break ( 80 min. )
Thu, Mar 2 PM 
13:30 - 14:45
(14) 13:30-13:55 [Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture VLD2016-115
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
(15) 13:55-14:20 [Invited Talk]
IP Timing Constraints Promotion Challenges
-- A method to automatically generate SoC Timing Constraints --
Tatsuya Nakae, Ichiro Shiihara (Socionext)
(16) 14:20-14:45 [Invited Talk]
Fast Monte Carlo based timing yield calculation via line sampling VLD2016-117
Hiromitsu Awano (UTokyo), Takashi Sato (Kyoto Univ.)
  14:45-15:00 Break ( 15 min. )
Thu, Mar 2 PM 
15:00 - 16:40
(17) 15:00-15:25 Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis VLD2016-118 Xiaoguang Li, Mineo Kaneko (JAIST)
(18) 15:25-15:50 Optimum Temperature Dependent Timing Skew for Temperature Aware Design VLD2016-119 Makoto Soga, Mineo Kaneko (JAIST)
(19) 15:50-16:15 MILP Approach to Skew-Aware High Level Synthesis VLD2016-120 Kai Shimura, Mineo Kaneko (JAIST)
(20) 16:15-16:40 An algorithm to compute covariance for finding distribution of the maximum VLD2016-121 Daiki Azuma, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.), Takashi Kambe (Kinki Univ.)
Fri, Mar 3 AM 
09:00 - 10:15
(21) 09:00-09:25 Dynamic Power Optimization for Asynchronous Circuits with Bundled-data Implementation based on the Mobility of Operations VLD2016-122 Shunya Hosaka, Hiroshi Saito (Aizu Univ)
(22) 09:25-09:50 A precise state-of-charge estimation system of primary battery for IoT devices VLD2016-123 Hirofumi Shioura, Naoki Yoshida, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.)
(23) 09:50-10:15 Using model-based design for EV batteries perfect for system development VLD2016-124 Tomoki Abe, Ryo Ueno, Lie Lin, Masahiro Fukui (Ritsumeikan Univ.)
  10:15-10:30 Break ( 15 min. )
Fri, Mar 3 PM 
10:30 - 11:45
(24) 10:30-10:55 A design method of nMOS dynamic shift registers for driver circuit of small liquid crystal display VLD2016-125 Youngtai Kang, Shuji Tsukiyama, Shinji Higa (Chuo Univ.)
(25) 10:55-11:20 A Study on LSI implementation of FEC for high-speed optical transmission VLD2016-126 Susumu Hirano, Kazuo Kubo, Hideo Yoshida, Kenji Ishii, Kenya Sugihara, Takashi Sugihara, Koji Miyanohana, Hirohide Nozaki, Noriyuki Minegishi (Mitsubishi Elec.)
(26) 11:20-11:45 Optimization of Parallel Prefix Adder Using Simulated Annealing VLD2016-127 Takayuki Moto, Mineo Kaneko (JAIST)
  11:45-13:00 Lunch Break ( 75 min. )
Fri, Mar 3 PM 
13:00 - 14:15
(27) 13:00-13:25 An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application VLD2016-128 Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
(28) 13:25-13:50 Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths VLD2016-129 Junghoon Oh, Mineo Kaneko (JAIST)
(29) 13:50-14:15 Architecture of Multiply-Accumulate Operation with Stochastic Iteration VLD2016-130 Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Daisuke Fukuda (Fujitsu Laboratories)
E-: d- 
Announcement See also VLD's homepage:

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