Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IPSJ-SLDM, VLD |
2012-05-30 14:30 |
Fukuoka |
Kitakyushu International Conference Center |
Task Allocation Optimization Method Using SA Method to Automatically Set Starting Temperature for Multi-Processor System Yuichiro Yanabu, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) VLD2012-1 |
Recently, Multi-Processor System is widely used for huge applications such as image and multimedia processing. To reduce... [more] |
VLD2012-1 pp.1-6 |
IPSJ-SLDM, VLD |
2012-05-30 14:55 |
Fukuoka |
Kitakyushu International Conference Center |
Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2 |
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] |
VLD2012-2 pp.7-12 |
IPSJ-SLDM, VLD |
2012-05-30 15:20 |
Fukuoka |
Kitakyushu International Conference Center |
Write Control Method Based on State Transition for Magnetic Flip-Flop Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2012-3 |
In this manuscript, we propose a write control method for nonvolatile MFF(Magnetic Flip--Flop). MFF enables leakage powe... [more] |
VLD2012-3 pp.13-18 |
IPSJ-SLDM, VLD |
2012-05-30 15:45 |
Fukuoka |
Kitakyushu International Conference Center |
High-level Design Debugging Using Potential Dependence Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-4 |
As high-level design draws more attention and has been adopted more widely, verification and debugging for high- level d... [more] |
VLD2012-4 pp.19-24 |
IPSJ-SLDM, VLD |
2012-05-30 16:20 |
Fukuoka |
Kitakyushu International Conference Center |
[Invited Talk]
How to Mitigate Reliability-related Issues on Nano-scaled LSIs Kazutoshi Kobayashi (KIT) VLD2012-5 |
According to aggressive process scaling, reliability issues on
semiconductor devices are becoming dominant such as vari... [more] |
VLD2012-5 pp.25-30 |
IPSJ-SLDM, VLD |
2012-05-31 09:30 |
Fukuoka |
Kitakyushu International Conference Center |
Sub-path delay estimation for reconvergent path Seiya Nagatsuka, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2012-6 |
[more] |
VLD2012-6 pp.31-36 |
IPSJ-SLDM, VLD |
2012-05-31 09:55 |
Fukuoka |
Kitakyushu International Conference Center |
A Placement Method on Overlapped Printed-Wiring-Boards Tetsuya Matsuura, Kunihiro Fujiyoshi (TUAT) VLD2012-7 |
In undersized manufacturing products,
some PWBs (Printed Wiring Boards) are installed with overlapping.
The distance... [more] |
VLD2012-7 pp.37-42 |
IPSJ-SLDM, VLD |
2012-05-31 10:20 |
Fukuoka |
Kitakyushu International Conference Center |
A Comparator Energy Model Considering Shallow Trench Isolation by Geometric Programming Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake (Kitakyushu Univ.) VLD2012-8 |
In low power analog circuit designs, the current variation caused by the STI stress must be taken into
account. In this... [more] |
VLD2012-8 pp.43-48 |
IPSJ-SLDM, VLD |
2012-05-31 10:55 |
Fukuoka |
Kitakyushu International Conference Center |
Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2012-9 |
This paper proposes a design support tool set for asynchronous circuits with bundled-data implemen-tation which are impl... [more] |
VLD2012-9 pp.49-54 |
IPSJ-SLDM, VLD |
2012-05-31 11:20 |
Fukuoka |
Kitakyushu International Conference Center |
Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) VLD2012-10 |
Statistical model checking is a method to analyze systems where variables have some uncertainty. It can be used to check... [more] |
VLD2012-10 pp.55-60 |