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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2011)
Search Results: Keywords 'from:2011-09-26 to:2011-09-26'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2011-09-26 14:00 |
Fukushima | University of Aizu | A transistor-level symmetrical layout generation method for analog device Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2011-40 |
[more] | VLD2011-40 pp.1-4 |
| VLD | 2011-09-26 14:25 |
Fukushima | University of Aizu | CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects Yu Zhang, Gong Chen, Qing Dong, Jing Li, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2011-41 |
[more] | VLD2011-41 pp.5-10 |
| VLD | 2011-09-26 14:50 |
Fukushima | University of Aizu | MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-42 |
The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challen... [more] | VLD2011-42 pp.11-16 |
| VLD | 2011-09-26 15:30 |
Fukushima | University of Aizu | Analytical Placement for Closed-Symmetrical Placement Yasuhiro Takashima, Yusuke Oya (Univ. of Kitakyushu) VLD2011-43 |
[more] | VLD2011-43 pp.17-22 |
| VLD | 2011-09-26 15:55 |
Fukushima | University of Aizu | On set pair routing problem Atsushi Takahashi (Osaka Univ.) VLD2011-44 |
In this manuscript, set pair routing problem in which connection requirements are given between a pair of terminal sets ... [more] | VLD2011-44 pp.23-28 |
| VLD | 2011-09-26 16:35 |
Fukushima | University of Aizu | [Invited Talk]
Bondage: A legal interconnect to define a reasonable placement Yoji Kajitani (Univ. of Kitakyushu) VLD2011-45 |
[more] | VLD2011-45 pp.29-30 |
| VLD | 2011-09-27 09:20 |
Fukushima | University of Aizu | A Reconfigurable Layout Method and Evaluation for Network on Chip Yuichi Nakamura (NEC) VLD2011-46 |
[more] | VLD2011-46 pp.31-36 |
| VLD | 2011-09-27 09:45 |
Fukushima | University of Aizu | Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47 |
FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blo... [more] | VLD2011-47 pp.37-42 |
| VLD | 2011-09-27 10:10 |
Fukushima | University of Aizu | A Design Method of Network-on-Chip Architecture for FPGA Hideki Katabami, Hiroshi Saito (Aizu Univ.) VLD2011-48 |
[more] | VLD2011-48 pp.43-48 |
| VLD | 2011-09-27 10:45 |
Fukushima | University of Aizu | A statistical evaluation of approximate methods for soft error tolerance analysis of combinational circuits Hidenori Ayabe, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2011-49 |
An approximate method which evaluates soft error tolerance with sampling has been proposed. There is an method to evalua... [more] | VLD2011-49 pp.49-54 |
| VLD | 2011-09-27 11:10 |
Fukushima | University of Aizu | Acceleration of Smith-Waterman Algorithm using a Pipelined Array Processor Asuka Tanaka, Shizuka Ishikawa, Toshiaki Miyazaki (Univ. of Aizu) VLD2011-50 |
Smith-Waterman algorithm is widely used for sequence alignment in bioinformatics. In this paper, a linear array processo... [more] | VLD2011-50 pp.55-59 |
| VLD | 2011-09-27 11:35 |
Fukushima | University of Aizu | Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis Keisuke Inoue, Mineo Kaneko (JAIST) VLD2011-51 |
[more] | VLD2011-51 pp.61-66 |
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