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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2008)

Search Results: Keywords 'from:2008-05-08 to:2008-05-08'

[Go to Official VLD Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2008-05-08
13:30
Hyogo Kobe Univ. [Invited Talk] HW/SW Co-verification Method Using FPGAs
Yuichi Nakamura, Kouhei Hosokawa (NEC) VLD2008-1
 [more] VLD2008-1
pp.1-6
VLD, IPSJ-SLDM 2008-05-08
14:45
Hyogo Kobe Univ. Checker Circuit Generation for System Verilog Assertions in Prototyping Verification
Mengru Wang, Shinji Kimura (Waseda Univ.) VLD2008-2
Reduction of verification period is the crucial problem in the recent LSI designs, and prototyping/emulation technologie... [more] VLD2008-2
pp.7-12
VLD, IPSJ-SLDM 2008-05-08
15:10
Hyogo Kobe Univ. Checker Generation of Assertions with Local Variables for Model Checking
Sho Takeuchi, Kiyoharu Hamaguchi, Yosuke Kakiuchi, Toshinobu Kashiwabara (Osaka Univ.)
To perform functional formal verification, model checking for
assertions has been used. It is difficult, however, to... [more]
VLD2008-3
pp.13-18
VLD, IPSJ-SLDM 2008-05-08
15:50
Hyogo Kobe Univ. Improvement Technique of Binding for Multiplexer Reduction
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.)
In Behavioral Synthesis for resource shared architecture, multiplexers are inserted before registers andfunctional units... [more] VLD2008-4
pp.19-24
VLD, IPSJ-SLDM 2008-05-08
16:15
Hyogo Kobe Univ. Radix-2 Butterfly Circuit Architecture Using Selector Logic
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) VLD2008-5
An arithmetic circuit using selector logic has been proposed,
as a high computational approach for processing.
In thi... [more]
VLD2008-5
pp.25-30
VLD, IPSJ-SLDM 2008-05-08
16:40
Hyogo Kobe Univ. Improvement of swtching activity aware algorithm for prefix graph synthesis
Taeko Matsunaga, Shinji Kimura (Waseda Univ), Yusuke Matsunaga (Kyushu Univ)
 [more] VLD2008-6
pp.31-36
VLD, IPSJ-SLDM 2008-05-09
10:00
Hyogo Kobe Univ. [Invited Talk] NoizeProblems in LSI Design:Challenges and Approaches
Makoto Nagata (Kobe Univ.)
Digital designs intending high-speed and low-power consumption necessarily deal with dynamic power supply noise, for suc... [more] VLD2008-7
pp.1-6
VLD, IPSJ-SLDM 2008-05-09
11:15
Hyogo Kobe Univ. Fast Wire Length Estimation in Obstructive Block Placement
Shuting Li (Univ. of Kitakyushu), Tan Yan (Univ. of Illinois at Urbana-Champaign), Yasuhiro Takashima, Hiroshi Murata (Univ. of Kitakyushu) VLD2008-8
IP-reuse can enhance the design productivity only if the design methodology treats the IPs in a proper way. Especially i... [more] VLD2008-8
pp.7-12
VLD, IPSJ-SLDM 2008-05-09
11:40
Hyogo Kobe Univ. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) VLD2008-9
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shr... [more] VLD2008-9
pp.13-18
VLD, IPSJ-SLDM 2008-05-09
13:30
Hyogo Kobe Univ. Fine-Grained Power Gating Based on the Controlling Value of Logic Gates
Lei Chen (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) VLD2008-10
Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating... [more] VLD2008-10
pp.19-24
VLD, IPSJ-SLDM 2008-05-09
13:55
Hyogo Kobe Univ. A Sub 100 mW H.264/AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding
Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
 [more] VLD2008-11
pp.25-30
VLD, IPSJ-SLDM 2008-05-09
14:35
Hyogo Kobe Univ. A Dependable SRAM with high-reliability mode and high-speed mode.
Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit (QoB)” for i... [more] VLD2008-12
pp.31-36
VLD, IPSJ-SLDM 2008-05-09
15:00
Hyogo Kobe Univ. On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints
Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-13
Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded
system at a c... [more]
VLD2008-13
pp.37-42
 Results 1 - 13 of 13  /   
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