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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2017)
Search Results: Keywords 'from:2018-02-28 to:2018-02-28'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS (Joint) |
2018-02-28 09:30 |
Okinawa | Okinawa Seinen Kaikan | On Fast Computation of RBF Approximate Function by FPGA Implementation Shogo Masuda, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)  VLD2017-89 |
Radial basis functions (RBFs) are used for function fitting (approximation) of discrete data in various fields such as m... [more] | VLD2017-89 pp.1-6 |
| VLD, HWS (Joint) |
2018-02-28 09:55 |
Okinawa | Okinawa Seinen Kaikan | On Memory Size Reduction of Programmable Hardware for Random Forest based Network Intrusion Detection Binbin Xue, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2017-90 |
In our previous research, we proposed dedicated programmable hardware of random forest based NIDSs. In this research, we... [more] | VLD2017-90 pp.7-12 |
| VLD, HWS (Joint) |
2018-02-28 10:20 |
Okinawa | Okinawa Seinen Kaikan | k-Nearest Neighbor Search Hardware Using Locality Sensitive Hashing for High-Dimensional Data Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) VLD2017-91 |
Recently, k-nearest neighbor search is frequently used in the field of pattern recognition, clustering,etc. However, f... [more] |
VLD2017-91 pp.13-18 |
| VLD, HWS (Joint) |
2018-02-28 11:00 |
Okinawa | Okinawa Seinen Kaikan | A fast routing method for multi-terminal nets using constraint satisfaction problem Saki Yamaguchi, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2017-92 |
In this paper, we propose a fast routing method using constraint satisfaction problem (CSP) for multi-terminal nets. I... [more] |
VLD2017-92 pp.19-24 |
| VLD, HWS (Joint) |
2018-02-28 11:25 |
Okinawa | Okinawa Seinen Kaikan | Amoeba-inspired SAT Solvers on FPGA through High Level Synthesis Hoang Ngoc Anh Nguyen (Tokyo Tech), Masashi Aono (Keio Univ.), Yuko Hara-Azumi (Tokyo Tech) VLD2017-93 |
[more] | VLD2017-93 pp.25-30 |
| VLD, HWS (Joint) |
2018-02-28 11:50 |
Okinawa | Okinawa Seinen Kaikan | Systematic Analysis Framework of Variables Significance towards Approximate Computing Sara Ayman Metwalli, Yuko Hara-Azumi (Tokyo Tech) VLD2017-94 |
[more] | VLD2017-94 pp.31-36 |
| VLD, HWS (Joint) |
2018-02-28 13:30 |
Okinawa | Okinawa Seinen Kaikan | Random Testing of Android Virtual Machine by Valid Dex File Generation Hirofumi Ikeo, Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2017-95 |
[more] | VLD2017-95 pp.37-42 |
| VLD, HWS (Joint) |
2018-02-28 13:55 |
Okinawa | Okinawa Seinen Kaikan | Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2017-96 pp.43-48 |
| VLD, HWS (Joint) |
2018-02-28 14:20 |
Okinawa | Okinawa Seinen Kaikan | Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2017-97 |
We develop a loop flattening tool for designing hardware with high level synthesis. When loop pipelining is applied to ... [more] | VLD2017-97 pp.49-54 |
| VLD, HWS (Joint) |
2018-02-28 15:00 |
Okinawa | Okinawa Seinen Kaikan | A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction Hirofumi Ihara, Takashi Imagawa (Ritumeikan Univ), Hiroki Uesaka, Shingo Kokami, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ), Hiroyuki Ochi (Ritumeikan Univ) VLD2017-98 |
Frame interpolation is one of methods to realize wireless transmission of high frame-rate and high resolution video unde... [more] | VLD2017-98 pp.55-60 |
| VLD, HWS (Joint) |
2018-02-28 15:25 |
Okinawa | Okinawa Seinen Kaikan | Architecture of Full-HD 60-fps Real-time Optical Flow Processor Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-99 |
This paper describes the architecture design of Full-HD 60fps real-time optical flow processor. In this processor, the W... [more] | VLD2017-99 pp.61-66 |
| VLD, HWS (Joint) |
2018-02-28 15:50 |
Okinawa | Okinawa Seinen Kaikan | A Study of Acceleration Optimization for an EV Cart with a Lithium-ion Battery Haruya Fujii, Yoshiki Tsuchida, Tomoki Abe, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.) VLD2017-100 |
In recent years, electric vehicles (EV) are spreading rapidly due to energy and environmental problems. Lithium ion accu... [more] | VLD2017-100 pp.67-72 |
| VLD, HWS (Joint) |
2018-02-28 16:30 |
Okinawa | Okinawa Seinen Kaikan | Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults Cheng Ma, Mineo Kaneko (JAIST) VLD2017-101 |
The report treats the reconfiguration-based fault-tolerance for FPGA applications, and proposes a method of finding a ch... [more] | VLD2017-101 pp.73-78 |
| VLD, HWS (Joint) |
2018-02-28 16:55 |
Okinawa | Okinawa Seinen Kaikan | Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2017-102 |
Among several problems with miniaturization of LSIs, soft-errors are one of serious problems to make reliability worse. ... [more] | VLD2017-102 pp.79-84 |
| VLD, HWS (Joint) |
2018-02-28 17:20 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103 |
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] | VLD2017-103 pp.85-90 |
| VLD, HWS (Joint) |
2018-02-28 17:45 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104 |
Moore's Law has been miniaturizing integrated circuits, which can make a lot of high performance devices such as PCs an... [more] |
VLD2017-104 pp.91-96 |
| VLD, HWS (Joint) |
2018-03-01 09:00 |
Okinawa | Okinawa Seinen Kaikan | A Study of Lithography Hotspot Detection Method Based on Feature Vectors Considering Distances between Wires Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2017-105 |
In lithography, which is one of the LSI fabrication processes, a layout pattern with a high failure probability is calle... [more] | VLD2017-105 pp.97-102 |
| VLD, HWS (Joint) |
2018-03-01 09:25 |
Okinawa | Okinawa Seinen Kaikan | Efficient Generation of Lithography Hotspot Detector based on Transfer Learning Shuhei Suzuki, Yoichi Tomioka (UoA) VLD2017-106 |
As semiconductor features shrink in size, the fidelity of the layout pattern transferred onto the wafer decreases. A layo... [more] | VLD2017-106 pp.103-108 |
| VLD, HWS (Joint) |
2018-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2017-107 pp.109-114 |
| VLD, HWS (Joint) |
2018-03-01 10:30 |
Okinawa | Okinawa Seinen Kaikan | A Motif Extraction Method Using Monte-Carlo Tree Search and its Experimental Evaluation Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2017-108 |
Discovering a similar substring from multiple strings is called motif extraction. It is used in various fields including... [more] | VLD2017-108 pp.115-120 |
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