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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2016)
Search Results: Keywords 'from:2016-11-28 to:2016-11-28'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | A Design Method of Circuits to Generate Stochastic Numbers with the Minimum Inputs Ritsuko Muguruma, Shigeru Yamashita (Ritsmeikan Univ.)  VLD2016-44 DC2016-38 |
Stochastic Computing (SC) is an unconventional calculation method using Stochastic Numbers (SNs) which are bit-streams r... [more] | VLD2016-44 DC2016-38 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Scheduling of Malleable Fork-Join Tasks Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2016-45 DC2016-39 |
This paper studies scheduling of malleable fork-join tasks. In our scheduling problem, each task can be partitioned into... [more] | VLD2016-45 DC2016-39 pp.7-11 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 12:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | 2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.) VLD2016-46 DC2016-40 |
This report proposes L1L5-type 2-step charge pump circuit that is suitable for boosting efficiently the subthreshold inp... [more] | VLD2016-46 DC2016-40 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:10 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB) Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech) VLD2016-47 DC2016-41 |
Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with di... [more] | VLD2016-47 DC2016-41 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:35 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-48 DC2016-42 |
Recently, the logic circuits are implemented to FPGA in many fields. To achieve faster circuits, a design flow to imple... [more] |
VLD2016-48 DC2016-42 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43 |
According to the Moore's law, LSIs are miniaturized and the reliability of LSIs is degraded. To improve the tolerance ... [more] |
VLD2016-49 DC2016-43 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:40 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44 |
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] | VLD2016-50 DC2016-44 pp.37-41 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:05 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-51 DC2016-45 |
We evaluate tolerance for soft errors of FFs on a 28/65 nm FDSOI. We fabricated three different layouts of non-redundant... [more] | VLD2016-51 DC2016-45 pp.43-48 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.) VLD2016-52 DC2016-46 |
We propose a circuit analysis method using the bimodal RTN (random telegraph noise) model of the defect-centric distri... [more] |
VLD2016-52 DC2016-46 pp.49-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design for 3-Demensional Sound Processor using a High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) RECONF2016-40 |
High quality sound systems are penetrated into our lifestyle in various fields. In recent years, Minimized audio spot ge... [more] | RECONF2016-40 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:40 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Variable Pipeline Ultra Low-power Coarse Grained Reconfigurable Accelelator Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano (Keio Univ.) RECONF2016-41 |
[more] | RECONF2016-41 pp.7-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:05 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | A Novel Merge Network for FPGA Sorting Accelerators Makoto Saitoh, Susumu Mashimo, Thiem Van Chu, Kenji Kise (Tokyotech) RECONF2016-42 |
[more] | RECONF2016-42 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT) RECONF2016-43 |
The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. ... [more] |
RECONF2016-43 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:05 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | RECONF2016-44 |
[more] | RECONF2016-44 pp.25-28 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:55 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Development of power estimation tool for three dimensional FPGA Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-46 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2016-46 pp.35-40 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 11:20 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Preliminary experimental platform for FlexPower FPGA evaluation Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike (AIST) RECONF2016-47 |
[more] | RECONF2016-47 pp.41-46 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-53 DC2016-47 |
We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper des... [more] | VLD2016-53 DC2016-47 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:50 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit Koki Ito, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-55 DC2016-49 |
(To be available after the conference date) [more] | VLD2016-55 DC2016-49 pp.67-72 |
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