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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2015)

Search Results: Keywords 'from:2016-01-19 to:2016-01-19'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 34  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
10:40		 Kanagawa Hiyoshi Campus, Keio University Circuit Design of Reconfigurable Logic and Comparison of the Methods
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) VLD2015-77 CPSY2015-109 RECONF2015-59		  [more] VLD2015-77 CPSY2015-109 RECONF2015-59
pp.1-6
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
11:05		 Kanagawa Hiyoshi Campus, Keio University FPGA routing structure based on H-Tree topology
Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2015-78 CPSY2015-110 RECONF2015-60		 FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resour... [more] VLD2015-78 CPSY2015-110 RECONF2015-60
pp.7-12
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
11:30		 Kanagawa Hiyoshi Campus, Keio University Pipelining in Coarse Grained Reconfigurable Accelerator CMA
Naoki Ando, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.) VLD2015-79 CPSY2015-111 RECONF2015-61		 (To be available after the conference date) [more] VLD2015-79 CPSY2015-111 RECONF2015-61
pp.13-18
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
11:55		 Kanagawa Hiyoshi Campus, Keio University A Low-Latency Batch Processing for Stream Data Using FPGA NIC
Kohei Nakamura, Ami Hayashi, Hiroki Matsutani (Keio Univ.) VLD2015-80 CPSY2015-112 RECONF2015-62		 (To be available after the conference date) [more] VLD2015-80 CPSY2015-112 RECONF2015-62
pp.19-24
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
13:30		 Kanagawa Hiyoshi Campus, Keio University Performance Evaluations on Reduction and Transformation of Spark Using GPU
Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani (Keio Univ.) VLD2015-81 CPSY2015-113 RECONF2015-63		 (To be available after the conference date) [more] VLD2015-81 CPSY2015-113 RECONF2015-63
pp.25-30
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
13:55		 Kanagawa Hiyoshi Campus, Keio University GPGPU Parallelization of a cerebral cortex model BESOM
Hidemoto Nakada, Tatsuhiko Inoue, Yuji Ichisugi (AIST) VLD2015-82 CPSY2015-114 RECONF2015-64		  [more] VLD2015-82 CPSY2015-114 RECONF2015-64
pp.31-36
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
14:20		 Kanagawa Hiyoshi Campus, Keio University GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2015-83 CPSY2015-115 RECONF2015-65		 In recent years，as the information，communication and sensing technologies advance，data streams have been continuously gr... [more] VLD2015-83 CPSY2015-115 RECONF2015-65
pp.37-42
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
16:55		 Kanagawa Hiyoshi Campus, Keio University Cost Estimation Method based on CPU Architecture for Relational Database Query Optimization
Tsuyoshi Tanaka (Tokyo Metropolitan Univ./Hitachi), Hiroshi Ishikawa (Tokyo Metropolitan Univ.) VLD2015-84 CPSY2015-116 RECONF2015-66		 Performance improvement and capacity enlargement of semiconductor record medium make the disk IO cost decrease and CPU c... [more] VLD2015-84 CPSY2015-116 RECONF2015-66
pp.67-72
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
17:20		 Kanagawa Hiyoshi Campus, Keio University Performance Improvement on In-Kernel NOSQL Cache for Range Queries
Korechika Tamura, Hiroki Matsutani (Keio Univ.) VLD2015-85 CPSY2015-117 RECONF2015-67		 (To be available after the conference date) [more] VLD2015-85 CPSY2015-117 RECONF2015-67
pp.73-78
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
17:45		 Kanagawa Hiyoshi Campus, Keio University FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams
Yoshimitsu Ogawa, Yasin Oge, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC) VLD2015-86 CPSY2015-118 RECONF2015-68		 In this report, we present an evaluation of Configurable Query Processing Hardware (CQPH) implemented on multiple FPGAs.... [more] VLD2015-86 CPSY2015-118 RECONF2015-68
pp.79-84
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
09:00		 Kanagawa Hiyoshi Campus, Keio University A Chip Evaluation of the Heat Generation in 3D stacked LSI
Tatsuya Wada, Kimiyosi Usami (Shibaura IT) VLD2015-87 CPSY2015-119 RECONF2015-69		 Heat is one of the problems in the three-dimensional stacking technology of LSI. We have developed a three-dimensional s... [more] VLD2015-87 CPSY2015-119 RECONF2015-69
pp.85-90
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
09:25		 Kanagawa Hiyoshi Campus, Keio University Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX
Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT) VLD2015-88 CPSY2015-120 RECONF2015-70		 Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] VLD2015-88 CPSY2015-120 RECONF2015-70
pp.91-96
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
09:50		 Kanagawa Hiyoshi Campus, Keio University Control Signal Extraction for Backward Sequential Clock Gating
Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-89 CPSY2015-121 RECONF2015-71		  [more] VLD2015-89 CPSY2015-121 RECONF2015-71
pp.97-102
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
12:00		 Kanagawa Hiyoshi Campus, Keio University [Fellow Memorial Lecture] Failure May teach Success -- In Computer Architecture Research based on Real hardware --
Hideharu Aamano (Keio Univ.) VLD2015-90 CPSY2015-122 RECONF2015-72		  [more] VLD2015-90 CPSY2015-122 RECONF2015-72
pp.121-124
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
14:15		 Kanagawa Hiyoshi Campus, Keio University Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis
Rie Soejima, Koji Okina, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2015-91 CPSY2015-123 RECONF2015-73		 In building-cube method (BCM), which is one of the adaptive mesh refinement, the computational region is divided into a ... [more] VLD2015-91 CPSY2015-123 RECONF2015-73
pp.125-130
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
14:40		 Kanagawa Hiyoshi Campus, Keio University FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler
Kohei Nagasu, Kentaro Sano (Tohoku Univ.), Fumiya Kono, Naohito Nakasato (The Univ. of Aizu) VLD2015-92 CPSY2015-124 RECONF2015-74		 Method of Splitting Tsunami (MOST) is a numerical solver of Shallow Water Equations (SWEs), which is used for forecastin... [more] VLD2015-92 CPSY2015-124 RECONF2015-74
pp.131-136
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
15:05		 Kanagawa Hiyoshi Campus, Keio University A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation
Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) VLD2015-93 CPSY2015-125 RECONF2015-75		 In many partial differential equation models used in various applications such as fluid analysis, their analytical solut... [more] VLD2015-93 CPSY2015-125 RECONF2015-75
pp.137-142
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
15:45		 Kanagawa Hiyoshi Campus, Keio University Topological Analysis of Low-Powered 3D-TESH Network
Faiz Al Faisal (JAIST), Hafizur Rahman (IIUM), Yasushi Inoguchi (JAIST) VLD2015-94 CPSY2015-126 RECONF2015-76		  [more] VLD2015-94 CPSY2015-126 RECONF2015-76
pp.143-148
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
16:10		 Kanagawa Hiyoshi Campus, Keio University An Efficient NoC with Decentralized Routers
Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) VLD2015-95 CPSY2015-127 RECONF2015-77		 (To be available after the conference date) [more] VLD2015-95 CPSY2015-127 RECONF2015-77
pp.149-154
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-20
16:35		 Kanagawa Hiyoshi Campus, Keio University A performance evaluation of PEACH3
Takahiro Kaneda, Chiharu Tsuruta (Keio Univ), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ) VLD2015-96 CPSY2015-128 RECONF2015-78		 A recent rapid increase of GPU performance makes GPGPU (General Purpose Computation using on GPUs) a mainstream of high ... [more] VLD2015-96 CPSY2015-128 RECONF2015-78
pp.155-160
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