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Technical Committee on VLSI Design Technologies (VLD)  (Searched in: 2014)

Search Results: Keywords 'from:2015-03-02 to:2015-03-02'

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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 32  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2015-03-02
13:00
Okinawa Okinawa Seinen Kaikan A Fast Lithographic Mask Correction Algorithm
Ahmd Awad, Atsushi Takahashi (Tokyo Institute of Technology) VLD2014-153
As technology nodes downscaling into sub-16 nm regime, the industry relies heavily on Optical Proximity
Correction (OP... [more]
VLD2014-153
pp.1-6
VLD 2015-03-02
13:25
Okinawa Okinawa Seinen Kaikan A cut-pattern reduction method for routing in Self-Aligned Double Patterning
Noriyuki Takahashi, Takeshi Ihara, Atsushi Takahashi (Tokyo Tech) VLD2014-154
In Self-Aligned Double Patterning (SADP),
a routing method that generates a SADP friendly routing pattern efficiently
... [more]
VLD2014-154
pp.7-12
VLD 2015-03-02
13:50
Okinawa Okinawa Seinen Kaikan Faster Numberlink solution using possibilities of topological routing
Yuichiro Tanaka, Atsushi Takahashi (Tokyo Tech) VLD2014-155
 [more] VLD2014-155
pp.13-18
VLD 2015-03-02
14:15
Okinawa Okinawa Seinen Kaikan Zero-weighted Cycle Finding Method for Exchanging Pin Pair on Set-Pair Rouitng
Yuta Nakatani, Atsushi Takahashi (Tokyo Tech) VLD2014-156
Set pair routing problem has connection requirements which are given between a pair of terminals. In set pair routing pr... [more] VLD2014-156
pp.19-24
VLD 2015-03-02
14:55
Okinawa Okinawa Seinen Kaikan Symmetrical Routing based on Set-pair Routing and Mixed Integer Programming
Masato Ito, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-157
This paper proposes a routing algorithm of high routability focusing on symmetrical routing used in analog layout. In a ... [more] VLD2014-157
pp.25-30
VLD 2015-03-02
15:20
Okinawa Okinawa Seinen Kaikan Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2014-158
 [more] VLD2014-158
pp.31-36
VLD 2015-03-02
15:45
Okinawa Okinawa Seinen Kaikan Studies on Representation of Stacked Rectangular Dissections for 3D-LSI Floorplan
Kazufumi Kogai, Kunihiro Fujiyoshi (TUAT) VLD2014-159
A stacked-rectangular-dissection, which consists of several rectangular-dissections, each of which is a rectangular area... [more] VLD2014-159
pp.37-41
VLD 2015-03-02
16:10
Okinawa Okinawa Seinen Kaikan A High Stability and Low Leakage Current Six-Transistor CMOS SRAM Employing a Single Low Supply Voltage
Nobuaki Kobayashi, Ryusuke Ito, Koji Motojima, Tadayoshi Enomoto (Chuo Univ.) VLD2014-160
 [more] VLD2014-160
pp.43-48
VLD 2015-03-03
08:50
Okinawa Okinawa Seinen Kaikan A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture
Song Bian, Michihiro Shintani (Kyoto Univ.), Zheng Wang (RWTH Aachen Univ.), Masayuki Hiromoto (Kyoto Univ.), Anupam Chattopadhyay (Nanyang Tech. Univ.), Takashi Sato (Kyoto Univ.) VLD2014-161
 [more] VLD2014-161
pp.49-54
VLD 2015-03-03
09:15
Okinawa Okinawa Seinen Kaikan A low-power soft error tolerant latch scheme
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2014-162
In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable pr... [more] VLD2014-162
pp.55-60
VLD 2015-03-03
09:40
Okinawa Okinawa Seinen Kaikan Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-163
We analyze the efficiency of the design methodology by using circuit
simulations. The design methodology which consider... [more]
VLD2014-163
pp.61-66
VLD 2015-03-03
10:20
Okinawa Okinawa Seinen Kaikan ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths
Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-164
As the device size decreases, reliability degradation caused by soft-errors has become one of the greatest issues in VLS... [more] VLD2014-164
pp.67-72
VLD 2015-03-03
10:45
Okinawa Okinawa Seinen Kaikan Generation of Asynchronous Circuits from a High-level Synthesis Tool
Taichi Komine, Hiroshi Saito (University of Aizu) VLD2014-165
 [more] VLD2014-165
pp.73-78
VLD 2015-03-03
11:10
Okinawa Okinawa Seinen Kaikan A design of FIR filters using High Level Synthesis -- A automated design of FIR filters --
Ryo Yamamoto, Naoya Okada, Noriyuki Minegishi (MELCO) VLD2014-166
 [more] VLD2014-166
pp.79-83
VLD 2015-03-03
11:35
Okinawa Okinawa Seinen Kaikan A Virtual/Real Combined Verification Method for FPGAs
Yoshimasa Ishino (MMS) VLD2014-167
The biggest advantage of FPGA is that can change the circuits at any time. Therefore, verification in virtual stage beco... [more] VLD2014-167
pp.85-89
VLD 2015-03-03
13:20
Okinawa Okinawa Seinen Kaikan [Invited Talk] Research in Industry and University for VLSI Design
Satoshi Goto (Waseda Univ.) VLD2014-168
 [more] VLD2014-168
pp.91-93
VLD 2015-03-03
14:35
Okinawa Okinawa Seinen Kaikan [Memorial Lecture] Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2014-169
This paper proposes an area efficient device parameter estimation method with sensitivity-configurable ring oscillator (... [more] VLD2014-169
p.95
VLD 2015-03-03
15:00
Okinawa Okinawa Seinen Kaikan [Memorial Lecture] A Performance Enhanced Dual-switch Network-on-Chip Architecture
Lian Zeng, Takahiro Watanabe (Waseda Univ.) VLD2014-170
Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critic... [more] VLD2014-170
pp.97-102
VLD 2015-03-03
15:25
Okinawa Okinawa Seinen Kaikan [Memorial Lecture] A Length Matching Routing Method for Disordered Pins in PCB Design
Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ.) VLD2014-171
In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obta... [more] VLD2014-171
pp.103-108
VLD 2015-03-03
15:50
Okinawa Okinawa Seinen Kaikan [Memorial Lecture] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2014-172
Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of micropro... [more] VLD2014-172
pp.109-114
 Results 1 - 20 of 32  /  [Next]  
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