Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:00 |
Kagoshima |
|
A VLSI algorithm for computing correctly rounded hypotenuse Hiroyuki Yataka, Naofumi Takagi (Kyoto Univ.) VLD2013-61 DC2013-27 |
Computation of the hypotenuse (2D euclidean norm) often appears in floating-point arithmetic in computer graphics andsci... [more] |
VLD2013-61 DC2013-27 pp.1-6 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:25 |
Kagoshima |
|
Fast distance calculation method for rooted tree with CUDA Hiroki Sakamoto, Yasuhiro Takashima (Univ. of Kitakyushu) VLD2013-62 DC2013-28 |
In this paper, we propose a fast distance calculation method for the rooted tree with CUDA.
In recent years, GPGPU has ... [more] |
VLD2013-62 DC2013-28 pp.7-12 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:50 |
Kagoshima |
|
Adjacent Common Centroid Placement for Analog IC Layout Design Kenichiro Murotatsu, Kunihiro Fujiyoshi (TUAT) VLD2013-63 DC2013-29 |
To improve immunity against process gradients, common centroid constraints, in which every pair of capacitors should be... [more] |
VLD2013-63 DC2013-29 pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 11:15 |
Kagoshima |
|
An Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan University Univ.), Tsung-Yi Ho (National Cheng Kung Univ.) VLD2013-64 DC2013-30 |
Sample preparation, which is a front-end process to produce droplets of the desired target concentrations from input rea... [more] |
VLD2013-64 DC2013-30 pp.19-24 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:00 |
Kagoshima |
|
[Invited Talk]
Minimal fab
-- One by one manufacturing of devices -- Shiro Hara, Hitoshi Maekawa, Shinichi Ikeda, Shizuka Nakano, Sommawan Khumpuang (AIST) |
[more] |
|
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:05 |
Kagoshima |
|
A Heuristic Design Method for Yield Improvement based on PPCs Shunichi Sanae, Yuko Hara-Azumi (NAIST), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST) VLD2013-65 DC2013-31 |
A PPC (Partially-Programmable Circuit) is a novel circuit model, which replaces some logic gates with LUTs (Look Up Tabl... [more] |
VLD2013-65 DC2013-31 pp.27-32 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:30 |
Kagoshima |
|
Fault-Tolerant Design with Less Overhead than DMR Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.) VLD2013-66 DC2013-32 |
This paper proposes two methods to increase yeild by using Partially-Programmable Circuits (PPCs)
that are proposed to ... [more] |
VLD2013-66 DC2013-32 pp.33-37 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima |
|
Suspicious timing error prediction using check points Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33 |
Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error ... [more] |
VLD2013-67 DC2013-33 pp.39-44 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 15:20 |
Kagoshima |
|
A controller design in high-level synthesis for multi-cycle transient fault tolerance Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2013-68 DC2013-34 |
This work discusses a design of the controller in a multi-cycle transient
fault tolerant system. It focuses especially ... [more] |
VLD2013-68 DC2013-34 pp.45-50 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:50 |
Kagoshima |
|
A Hardware/Software Simulator for NoC using SystemC and QEMU Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2013-69 DC2013-35 |
[more] |
VLD2013-69 DC2013-35 pp.63-68 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:00 |
Kagoshima |
|
A High-Speed FFT for a Solar Radio Burst Obvervation on a Radio Telescope Hiroki Nakahara, Youhei Chishiki (Kagoshima Univ.), Kazumasa Iwai (NAOJ), Hiroyuki Nakanishi (Kagoshima Univ.) RECONF2013-39 |
A radio telescope analyzes radio frequency(RF) received from celestial objects.
It consists of an antenna, a receiver, ... [more] |
RECONF2013-39 pp.1-6 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:25 |
Kagoshima |
|
An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD Kensuke Kushiyama, Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.) RECONF2013-40 |
The core routers forward packets by IP-lookup using longest prefix matching~(LPM) by using a content addressable memory~... [more] |
RECONF2013-40 pp.7-12 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:05 |
Kagoshima |
|
Improved via programmable structured ASIC VPEX3S
-- Improvement of basic logic element to improve operation speed -- Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-70 DC2013-36 |
We have been studying via programmable structured ASIC architecture “VPEX3(Via Programmable Logic using Exclusive-OR Arr... [more] |
VLD2013-70 DC2013-36 pp.75-80 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:30 |
Kagoshima |
|
New Via Programmable Architecture VPEX4 (1)
-- Development of new logic element for improvement of routability and power consumption -- Ryohei Hori, Taku Otani, Tatsuro Hitomi, Shota Ueguchi (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-71 DC2013-37 |
The Non-Recruring Engineering (NRE) cost of LSI is increasing drastically with the advances in LSI process and manufactu... [more] |
VLD2013-71 DC2013-37 pp.81-86 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 14:55 |
Kagoshima |
|
Evaluation of Via Programmable Device named VPEX using benchmark circuits Shota Ueguchi, Ryohei Hori, Taku Otani (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-72 DC2013-38 |
Non-Recurring engineering cost including photo-mask cost increases with LSI process minimization. We have been studied v... [more] |
VLD2013-72 DC2013-38 pp.87-92 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 08:50 |
Kagoshima |
|
Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.) CPM2013-108 ICD2013-85 |
A resistor ladder is an important circuit block for the parallel architecture analog-to-digital converters (ADCs). The o... [more] |
CPM2013-108 ICD2013-85 pp.1-6 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:15 |
Kagoshima |
|
Co-design for reducing power supply noises with On-die PDN Impedance Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86 |
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electro... [more] |
CPM2013-109 ICD2013-86 pp.7-12 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:40 |
Kagoshima |
|
The design of Via Programmable Analog(VPA) circuit and its performance evaluation compared to programmable analog circuit Keisuke Ueda, Ryohei Hori, Mitsuru Shiozaki, Toshio Kumamoto, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-110 ICD2013-87 |
Recently, programmable analog circuits are started to be used because initial development cost including mask cost is re... [more] |
CPM2013-110 ICD2013-87 pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:20 |
Kagoshima |
|
Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-111 ICD2013-88 |
Tamper-resistant devices require to protect cryptographic circuit from side-channel attacks such as power analysis (PA) ... [more] |
CPM2013-111 ICD2013-88 pp.19-24 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 10:45 |
Kagoshima |
|
Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks Takashi Nishimura, Syuuhei Sugaya, Akihiro Takeuchi, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-112 ICD2013-89 |
Physical unclonable function (PUF) has been proposed as tamper-resistant technique to protect secure device. The PUF ext... [more] |
CPM2013-112 ICD2013-89 pp.25-30 |