IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

Technical Committee on VLSI Design Technologies (VLD)  (2021 - )

Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech.) Vice Chair: Minako Ikeda (NTT)
Secretary: Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

[Go to Official VLD Homepage (Japanese)] 
 Schedule  (Sort by: Date Ascending)
 Results 1 - 4 of 4  /   
Date Place Topics Joint Deadline Select Menu
Mon, May 10, 2021
- Tue, May 11
Online   ICD, CPSY, DC, HWS, IPSJ-SLDM, IPSJ-ARC
(2nd)
 
  • Detailed Info.
       (Japanese)
     
  • Mon, Jul 5, 2021
    - Tue, Jul 6
    Online   SIP, CAS, MSS [Fri, May 7]
  • Regist. Closed
  • Adv. Program
  • Registration Fee 
  • Wed, Dec 1, 2021
    - Thu, Dec 2
    Online Design Gaia 2021 -New Field of VLSI Design- VLD, DC, RECONF, ICD, IPSJ-SLDM
    (Joint) [detail]
    [Fri, Sep 3]
  • Detailed Info.
       (Japanese)
  • Regist. Closed
  • Registration Fee 
  • Jan, 2022 (unfixed)
    -
    T.B.D. FPGA Applications, etc.
    Conference style (on-site/online/hybrid) is not yet decided.
    RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] [unfixed]
  • Registration Fee 
  •  Results 1 - 4 of 4  /   


    [Return to Top Page]

    [Return to IEICE Web Page]


    The Institute of Electronics, Information and Communication Engineers (IEICE), Japan