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Technical Committee on Silicon Device and Materials (SDM) (Searched in: 2015)
Search Results: Keywords 'from:2016-01-28 to:2016-01-28'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2016-01-28 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Experimental Study on Carrier Transport Properties in Extremely-Thin Body Ge-on-Insulator (GOI) p-MOSFETs with GOI Thickness Down to 2 nm Xiao Yu, Jian Kang, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo)  SDM2015-120 |
[more] | SDM2015-120 pp.1-4 |
| SDM | 2016-01-28 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Carrier Transport Analysis of High-Performance Poly-Si Nanowire Transistor Fabricated by Advanced SPC with Record-High Electron Mobility Minoru Oda, Kiwamu Sakuma, Yuuichi Kamimuta, Masumi Saitoh (Toshiba Corp.) SDM2015-121 |
High-performance poly-Si nanowire transistors were fabricated by Advanced SPC process, in which the process of forming a... [more] | SDM2015-121 pp.5-8 |
| SDM | 2016-01-28 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Understanding of BTI for Tunnel FETs Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yuki Ishikawa, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Yongxun Liu, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Takashi Matsukawa, Meishoku Masahara, Kazuhiko Endo (AIST) SDM2015-122 |
(To be available after the conference date) [more] | SDM2015-122 pp.9-12 |
| SDM | 2016-01-28 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Van der Waals Junctions of Layered 2D Materials for Functional Devices Tomoki Machida, Rai Moritani, Yohta Sata, Takehiro Yamaguchi, Miho Arai, Naoto Yabuki, Sei Morikawa, Satoru Masubuchi (Univ. of Tokyo), Keiji Ueno (Saitama Univ.) SDM2015-123 |
Recent advances in transfer techniques of atomic layers have enabled one to fabricate van der Waals junctions of two-dim... [more] | SDM2015-123 pp.13-16 |
| SDM | 2016-01-28 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
CMOS photonics technologies based on heterogeneous integration on Si Mitsuru Takenaka, Younghyun Kim, Jaehoon Han, Jian Kan, Yuki Ikku, Yongpeng Cheng, Jinkwon Park, SangHyeon Kim, Shinichi Takagi (Univ. of Tokyo) SDM2015-124 |
In this paper, we present heterogeneous integration of SiGe/Ge and III-V semiconductors on Si for electronic-photonic in... [more] | SDM2015-124 pp.17-20 |
| SDM | 2016-01-28 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125 |
[more] | SDM2015-125 pp.21-25 |
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| SDM | 2016-01-28 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Super Steep Subthreshold Slope PN-Body Tied SOI FET with Ultra Low Drain Voltage Jiro Ida (Kanazawa Institute of Technology) SDM2015-127 |
We have proposed the new type super steep subthreshold slope (SS) device of the PN-body tied SOI FET. The N region is in... [more] | SDM2015-127 pp.31-34 |
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