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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2009)
Search Results: Keywords 'from:2009-09-17 to:2009-09-17'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2009-09-17 13:00 |
Tochigi | Utsunomiya Univ. | Rea-time detection of rotated patterns using FPGA Yoshifumi Tanida, Tsutomu Maruyama (Tsukuba Univ.)  RECONF2009-19 |
In this paper, we describe an approach for real-time detection of rotated patterns in an image using FPGA. In many app... [more] |
RECONF2009-19 pp.1-6 |
| RECONF | 2009-09-17 13:25 |
Tochigi | Utsunomiya Univ. | Component Labeling on the FPGA using Few Logic Elements Yasuaki Ito, Koji Nakano (Hiroshima Univ.) RECONF2009-20 |
In this paper, we present a hardware connected component labeling algorithm which is a task that assigns unique IDs to ... [more] |
RECONF2009-20 pp.7-12 |
| RECONF | 2009-09-17 13:50 |
Tochigi | Utsunomiya Univ. | Performance Evaluation of Levenshtein-Distance Computation on One-Dimensional FPGA Array Cube Masato Yoshimi, Mitsunori Miki (Doshisha Univ.), Yuri Nishikawa, Akihiro Shitara, Hideharu Amano (Keio Univ.), Oskar Mencer (Imperial College London) RECONF2009-21 |
This report evaluates results of computing edit distance algorithm on Cube, a computation system using multiple FPGAs co... [more] | RECONF2009-21 pp.13-18 |
| RECONF | 2009-09-17 14:15 |
Tochigi | Utsunomiya Univ. | FPGA implementation and accuracy evaluation of a power-supply voltage control circuit Masato Soejima, Junya Sakemi, Yuichiro Shibata, Fujio Kurokawa, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ) RECONF2009-22 |
Demands for more steady and more efficient direct voltage power supplies have been increasing in the context of energy ... [more] |
RECONF2009-22 pp.19-24 |
| RECONF | 2009-09-17 14:50 |
Tochigi | Utsunomiya Univ. | Low-power oriented clustering and placement tools using routability for FPGAs Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-23 |
Power consumption of Field Programmable Gate Arrays (FPGAs) is larger than Application Specific Integrated Circuits (ASI... [more] | RECONF2009-23 pp.25-30 |
| RECONF | 2009-09-17 15:15 |
Tochigi | Utsunomiya Univ. | An analysis of frequency in the use LUT logic functions based on P-equivalence class Masaki Shintani, Kota Kato, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-24 |
Look-up table (LUT) has many SRAM and multiplexers, and you can implement any logic function to LUTs if the number of it... [more] | RECONF2009-24 pp.31-36 |
| RECONF | 2009-09-17 15:40 |
Tochigi | Utsunomiya Univ. | Design and Fabrication of Flex Power FPGA with Power Reconfigurability Masakazu Hioki (AIST), Takashi Kawanami (Kanazawa Inst. of Tech.), Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) RECONF2009-25 |
Our research group has evaluated “Flex Power FPGA” which can reconfigure the power from the viewpoint of software and ha... [more] | RECONF2009-25 pp.37-42 |
| RECONF | 2009-09-17 16:05 |
Tochigi | Utsunomiya Univ. | Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.) RECONF2009-26 |
One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is its low dynamic power consump... [more] |
RECONF2009-26 pp.43-48 |
| RECONF | 2009-09-17 16:40 |
Tochigi | Utsunomiya Univ. | [Invited Talk]
YAWARA: A Self-Optimizing Computer System Project Takanobu Baba, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) RECONF2009-27 |
The YAWARA project aims at an extreme optimization system that reconfigures both hardware and software at run-time. This... [more] | RECONF2009-27 pp.49-54 |
| RECONF | 2009-09-18 09:00 |
Tochigi | Utsunomiya Univ. | A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28 |
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] | RECONF2009-28 pp.55-60 |
| RECONF | 2009-09-18 09:25 |
Tochigi | Utsunomiya Univ. | Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-29 |
We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is th... [more] | RECONF2009-29 pp.61-66 |
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| RECONF | 2009-09-18 10:25 |
Tochigi | Utsunomiya Univ. | A Study of Scalable Prototyping System with Small-sized FPGAs Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech) RECONF2009-31 |
In order to practically simulate many-core processor, the authors proposed ScalableCore which is a hardware simulator. ... [more] |
RECONF2009-31 pp.73-78 |
| RECONF | 2009-09-18 10:50 |
Tochigi | Utsunomiya Univ. | An FPGA-based Tiny Processing System for Small Embedded System and Education Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto (Hiroshima Univ) RECONF2009-32 |
The main contribution of this paper is to present a simple, scalable, and portable tiny processing system which can be ... [more] |
RECONF2009-32 pp.79-84 |
| RECONF | 2009-09-18 11:15 |
Tochigi | Utsunomiya Univ. | A Study of Topology-adaptive Network-on-Chip for Many-Core SoC Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.) RECONF2009-33 |
[more] | RECONF2009-33 pp.85-90 |
| RECONF | 2009-09-18 11:40 |
Tochigi | Utsunomiya Univ. | Packet Capturing and Routing Functions on a Network Testbed GtrcNET-10p3 Yuetsu Kodama, Ryousei Takano, Fumihiro Okazaki, Tomohiro Kudoh (AIST) RECONF2009-34 |
We developed a network testbed GtrcNET-10p3 which consisted of a large scale FPGA and 10GbE interfaces. We used it for ... [more] |
RECONF2009-34 pp.91-96 |
| RECONF | 2009-09-18 13:10 |
Tochigi | Utsunomiya Univ. | High-density Implementation for Reconfigurable Device MPLD Hiroaki Toguchi, Masanori Asaeda, Yutaro Oda, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN CO.LTD) RECONF2009-35 |
In recent years, a lot of Programmable Logic Device (PLD) such as Field Programmable Gate Array (FPGA) has been used. As... [more] | RECONF2009-35 pp.97-102 |
| RECONF | 2009-09-18 13:35 |
Tochigi | Utsunomiya Univ. | An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36 |
This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (L... [more] | RECONF2009-36 pp.103-108 |
| RECONF | 2009-09-18 14:00 |
Tochigi | Utsunomiya Univ. | A writer system not using an imaging lens for 4-context programmable optically reconfigurable gate arrays Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) RECONF2009-37 |
[more] | RECONF2009-37 pp.109-112 |
| RECONF | 2009-09-18 14:35 |
Tochigi | Utsunomiya Univ. | FPGA-based Stream Computation for HPC
-- Designing and Evaluating a Scalable Pipeline-Module for 2D Jacobi Computation -- Kentaro Sano, Yoshiaki Hatsuda, Yasuhiro Otsubo, Satoru Yamamoto (Tohoku Univ.) RECONF2009-38 |
[more] | RECONF2009-38 pp.113-118 |
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