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Technical Committee on Reconfigurable Systems (RECONF)  (Searched in: 2014)

Search Results: Keywords 'from:2014-11-26 to:2014-11-26'

[Go to Official RECONF Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 20 of 65  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:15
Oita B-ConPlaza A study on automated arithmetic pipeline design on multi-FPGA systems
Yusuke Hirai, Katsuki Kyan, Makoto Arakaki (Univ. Ryukyus), Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. Ryukyus) RECONF2014-34
Computational fluid dynamics (CFD), a powerful tool for aircraft
design and other mechanical designs is a major applica... [more]
RECONF2014-34
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:40
Oita B-ConPlaza Implementation of Multi-dimensional FPGA array HPC system-Vocalise for Numerical simulation and its Performance Evaluation
Jiang Li, Hiromasa Kubo, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT) RECONF2014-35
In recent years, the HPC systems with FPGAs increase.
We have proposed the HPC system Vocalise with FPGA array.
The ... [more]
RECONF2014-35
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
10:05
Oita B-ConPlaza Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures
Hayate Okuhara, Hideharu Amano (Keio Univ.) RECONF2014-36
(To be available after the conference date) [more] RECONF2014-36
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
10:45
Oita B-ConPlaza Mobile robot system based on hw/sw Complex System using 3D FPGA-Array System "Vocalise"
Hiromasa Kubo, Jiang Li, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT) RECONF2014-37
Our laboratory has been developing the 3D FPGA-Array HPC system named “Vocalise”(Virtual Object by Configurable Array of... [more] RECONF2014-37
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
11:10
Oita B-ConPlaza An Image Recognition System Learning Feature Regions with Vocalise
Satoru Yokota, Jiang Li, Hiromasa Kubo, Masatoshi Sekine (TUAT) RECONF2014-38
Recently much attention has been paid to image recognition systems for mobile systems. Mobile systems are used in variou... [more] RECONF2014-38
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
11:35
Oita B-ConPlaza Efficient FPGA resource allocation for HOG-based human detection
Masahito Oishi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2014-39
In this paper, we discuss implementation for highly efficient and compact FPGA implementation of an image-based
real-ti... [more]
RECONF2014-39
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
14:45
Oita B-ConPlaza Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] VLD2014-72 DC2014-26
pp.3-8
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:10
Oita B-ConPlaza Analytical placement consistent with hierarchical structure constraints in analog floorplan
Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-73 DC2014-27
 [more] VLD2014-73 DC2014-27
pp.9-13
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:35
Oita B-ConPlaza An efficient calculation of RTN-induced SRAM failure probability
Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) VLD2014-74 DC2014-28
Failure rate degradation of an SRAM cell due to random telegraph noise (RTN) is calculated for the first time. An effic... [more] VLD2014-74 DC2014-28
pp.15-20
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
16:15
Oita B-ConPlaza General-Purpose Pattern Recognition Processor Based on the k Nearest-Neighbor Algorithm with High-Speed, Low-Power
Shogo Yamasaki, Toshinobu Akazawa, Fengwei An, Hans Juergen Mattausch (Hiroshima Univ.) VLD2014-75 DC2014-29
A learning and pattern recognition processors for the k nearest neighbor (k-NN) recognition algorithm using a nearest Eu... [more] VLD2014-75 DC2014-29
pp.21-26
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
16:40
Oita B-ConPlaza An FPGA Implementation of Real-Time Traffic-Sign Detection for Driver Assistance System
Masaharu Yamamoto, Anh-Tuan Hoang, Tetsushi Koide (Hiroshima Univ.) VLD2014-76 DC2014-30
In this paper, we propose a hardware-oriented speed traffic-sign recognition algorithm and its FPGA architecture in whic... [more] VLD2014-76 DC2014-30
pp.27-32
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
17:05
Oita B-ConPlaza Visual-Word Feature Transformation Architecture for Computer-Aided Diagnosis using Colorectal Endoscopic Images with NBI Magnification
Koki Sugi, Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.) VLD2014-77 DC2014-31
With the increase of colorectal cancer patients in recent years, the computer-aided diagnosis (CAD) system which support... [more] VLD2014-77 DC2014-31
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
17:30
Oita B-ConPlaza Hardware Design of Type Identifier based on Support Vector Machine for Computer-Aided Diagnosis of Colorectal Endoscopic Images
Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Tatsuya Shimizu, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka (Hiroshima Univ.) VLD2014-78 DC2014-32
With the increase of colorectal cancer patients in recent years, the needs of quantitative evaluation of colorectal canc... [more] VLD2014-78 DC2014-32
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:15
Oita B-ConPlaza Design of Flip-Flop with Timing Error Tolerance
Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] VLD2014-79 DC2014-33
pp.45-50
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:40
Oita B-ConPlaza Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits
Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34
The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be expl... [more] VLD2014-80 DC2014-34
pp.51-56
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
10:05
Oita B-ConPlaza An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-81 DC2014-35
As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error cor... [more] VLD2014-81 DC2014-35
pp.57-62
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
14:45
Oita B-ConPlaza Development and Evaluation of Pipelining of Heap-Sort Execution for Low-Latency Stream Data Processing
Yoshifumi Fujikawa, Tetsuro Hommura, Tadayuki Matsumura (Hitachi) CPSY2014-72
The feature of low latency is becoming important for applications of Stream Data Processing (SDP) such as HFT, and so is... [more] CPSY2014-72
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:10
Oita B-ConPlaza A Large Graph Segmentation Method for Triangle Counting
Tatsuhiro Hirano, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-73
We previously proposed a breadth-first-search (BFS) triangle counting method to fast get the triangle counts of a graph.... [more] CPSY2014-73
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
15:35
Oita B-ConPlaza Parallelization of Shortest Path Search on Various Platforms and Its Evaluation
Shuto Kurebayashi, Shinya Takamaeda, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-74
Since graph processing has irregular control flows and memory access patterns, its acceleration by the parallelization i... [more] CPSY2014-74
pp.13-18
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
16:15
Oita B-ConPlaza An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75
In recent years, high speed and high precision computing is increasingly needed.
Hardware support for IEEE754 compliant... [more]
CPSY2014-75
pp.19-23
 Results 1 - 20 of 65  /  [Next]  
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