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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2014)
Search Results: Keywords 'from:2014-09-18 to:2014-09-18'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2014-09-18 13:00 |
Hiroshima | [Invited Talk]
Architecture Development for the Real-time Computer-Aided Diagnosis of Colorectal Endoscopic Images with NBI Magnification Tetsushi Koide (Hiroshima Univ.)  RECONF2014-17 |
With the increase in patients of colorectal cancer in recent years, the requirement of the effective diagnostic support ... [more] | RECONF2014-17 pp.1-6 |
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| RECONF | 2014-09-18 14:10 |
Hiroshima | Prototype of fault tolerant FPGA using 65nm CMOS process Motoki Amagasaki, Takuya Kajiwara, Kentaro Fujisawa, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-18 |
我々はSoC（System on a Chip）に搭載されるFPGA-IP（Field Programmable Gate Array Intellectual Property）コアに焦点をあてたFT-FPGA（Fault Tolera... [more] |
RECONF2014-18 pp.7-12 |
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| RECONF | 2014-09-18 14:35 |
Hiroshima | A study of run-time fault detection mechanism for fault-tolerant FPGAs Kentaro Fujisawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-19 |
The fault detection is very important for high reliability system LSI. In this paper, we propose a dynamic fault detecti... [more] | RECONF2014-19 pp.13-18 |
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| RECONF | 2014-09-18 15:00 |
Hiroshima | Radiation tolerance of a holographic memory part on an optically reconfigurable gate array Retsu Moriwaki, Hiroyuki Ito (Shizuoka Univ.), Akira Maekawa (Kobe City College of Tech.), Minoru Watanabe (Shizuoka Univ.), Akifumi Ogiwara (Kobe City College of Tech.) RECONF2014-20 |
[more] | RECONF2014-20 pp.19-22 |
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| RECONF | 2014-09-18 15:45 |
Hiroshima | Challenge for Ultrafast 10K-Node NoC emulation on FPGA Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) RECONF2014-21 |
With thousands of cores in the near future NoC architectures, the simulation time is a serious problem that makes archit... [more] | RECONF2014-21 pp.23-28 |
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| RECONF | 2014-09-18 16:10 |
Hiroshima | Dynamically reconfigurable protocol-processing hardware for communications SoC Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu (NTT) RECONF2014-22 |
We propose an architecture of dynamically reconfigurable hardware for protocol processing (DRHPP) for a communications s... [more] | RECONF2014-22 pp.29-34 |
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| RECONF | 2014-09-18 16:35 |
Hiroshima | A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies Masato Inagi (Hiroshima City Univ.), Yuichi Nakamura (NEC), Yasuhiro Takashima (Univ. of Kitakyusyu), Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2014-23 |
[more] | RECONF2014-23 pp.35-40 |
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| RECONF | 2014-09-18 17:20 |
Hiroshima | On The Second Flex Power FPGA Chip with SOTB Transistors Hanpei Koike (AIST), Chao Ma (Meiji Univ.), Masakazu Hioki, Yasuhiro Ogasahara (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2014-24 |
[more] | RECONF2014-24 pp.41-46 |
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| RECONF | 2014-09-18 17:45 |
Hiroshima | Parallel-operation-oriented optically reconfigurable gate array Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) RECONF2014-25 |
[more] | RECONF2014-25 pp.47-50 |
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| RECONF | 2014-09-19 09:00 |
Hiroshima | [Invited Talk]
Research & Development of FPGA Applications in A Company Takefumi Miyoshi (e-trees.Japan) RECONF2014-26 |
[more] | RECONF2014-26 pp.51-56 |
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| RECONF | 2014-09-19 10:10 |
Hiroshima | Building a Mixed Software Hardware Pipeline on CPU-FPGA Platforms Takaaki Miyajima (Keio Univ.), David Thomas (ICL), Hideharu Amano (Keio Univ.) RECONF2014-27 |
This new toolchain for accelerating application on CPU-FPGA platforms, called Courier-FPGA, extracts runtime information... [more] | RECONF2014-27 pp.57-62 |
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| RECONF | 2014-09-19 10:35 |
Hiroshima | Evaluation and Implementation of the Calculation Feature to PEACH2 Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Univ. of Tokyo), Hideharu Amano (Keio Univ.) RECONF2014-28 |
[more] | RECONF2014-28 pp.63-68 |
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| RECONF | 2014-09-19 11:00 |
Hiroshima | GRAPE9-MPX: A development of an accelerator dedicated for arbitrary-precision arithmetic by the FPGA boards Shinji Motoki (KEK), Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Toshiyuki Fukushige, Atsushi Kawai (K & F Computing Research), Junichiro Makino (RIKEN/TITECH) RECONF2014-29 |
Higher order corrections in perturbative quantum field theory are required for precise theoretical analysis to investiga... [more] | RECONF2014-29 pp.69-74 |
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| RECONF | 2014-09-19 13:05 |
Hiroshima | Discussion for speed up of three-dimensional space imaging using sound waves Keiko Oda, Akira Kojima, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2014-30 |
In general, the most of methods for three-dimensional imaging using sound waves measure the distance of objects by analy... [more] | RECONF2014-30 pp.75-80 |
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| RECONF | 2014-09-19 13:30 |
Hiroshima | FPGA implementation of a Compact Processor Yukiyama for tiny SoC Yuichi Watanabe, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2014-31 |
This paper proposes a small soft-core processor architecture that can be mapped to a CPLD. This paper describes the det... [more] |
RECONF2014-31 pp.81-86 |
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| RECONF | 2014-09-19 14:15 |
Hiroshima | A Trial Hardware Design of a Recursive Function to Solve "OX game" by Code-Modification and High-Level Synthesis Masashi Ohno, Yu Nakahara, Tomonori Izumi, Lin Meng (Ritsumeikan Univ.) RECONF2014-32 |
[more] | RECONF2014-32 pp.87-92 |
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| RECONF | 2014-09-19 14:40 |
Hiroshima | Formal Verification System of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-33 |
Regardless of wide using of a formal verification methods, almost all of the methods limited to single-clock synchrounou... [more] | RECONF2014-33 pp.93-98 |
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