Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, ITE-IST |
2010-07-22 09:30 |
Osaka |
Josho Gakuen Osaka Center |
On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration Takushi Hashida, Hiroshi Matsumoto, Makoto Nagata (Kobe Univ.) ICD2010-21 |
On-chip waveform capture exhibits the resolution of 10 ps and 200 uV with 1024 steps, and SFDR of 63.2dB in 700-MHz sign... [more] |
ICD2010-21 pp.1-4 |
ICD, ITE-IST |
2010-07-22 09:55 |
Osaka |
Josho Gakuen Osaka Center |
Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.) ICD2010-22 |
[more] |
ICD2010-22 pp.5-9 |
ICD, ITE-IST |
2010-07-22 10:20 |
Osaka |
Josho Gakuen Osaka Center |
In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2010-23 |
[more] |
ICD2010-23 pp.11-14 |
ICD, ITE-IST |
2010-07-22 10:45 |
Osaka |
Josho Gakuen Osaka Center |
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) ICD2010-24 |
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] |
ICD2010-24 pp.15-20 |
ICD, ITE-IST |
2010-07-22 11:20 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
Digital Calibration and Correction Methods for CMOS-ADCs Shiro Dosho (Panasonic Corp.) ICD2010-25 |
[more] |
ICD2010-25 pp.21-30 |
ICD, ITE-IST |
2010-07-22 12:10 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
A 10b 50MS/s 820uW SAR ADC with on-chip digital calibration Sanroku Tsukamoto (Fujitsu Labs.) ICD2010-26 |
[more] |
ICD2010-26 pp.31-36 |
ICD, ITE-IST |
2010-07-22 14:00 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
Digitally-Assisted Analog Test Technology
-- Analog Circuit Test Technology in Nano-CMOS Era -- Haruo Kobayashi, Takahiro J. Yamaguchi (Gunma Univ.) ICD2010-27 |
This paper reviews current production testing issues for analog and
mixed-signal SoC, and discusses the following:
(i)... [more] |
ICD2010-27 pp.37-42 |
ICD, ITE-IST |
2010-07-22 14:50 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
Technical Trend of Multi-mode Multi-band RF Transceivers Hisayasu Sato (Renesas Electronics) ICD2010-28 |
This paper describes resent technology trend of multi-mode multi-band RF transceivers. Thanks to advanced CMOS technolog... [more] |
ICD2010-28 pp.43-48 |
ICD, ITE-IST |
2010-07-22 15:50 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29 |
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital conver... [more] |
ICD2010-29 pp.49-54 |
ICD, ITE-IST |
2010-07-23 09:15 |
Osaka |
Josho Gakuen Osaka Center |
Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply Tomochika Harada (Yamagata Univ.) ICD2010-30 |
[more] |
ICD2010-30 pp.55-60 |
ICD, ITE-IST |
2010-07-23 09:40 |
Osaka |
Josho Gakuen Osaka Center |
OTA Design Using gm/ID Lookup Table Methodology
-- Design optimization featuring settling time analysis -- Toru Kashimura, Takayuki Konishi, Shoichi Masui (Tohoku Univ.) ICD2010-31 |
Settling time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applic... [more] |
ICD2010-31 pp.61-66 |
ICD, ITE-IST |
2010-07-23 10:05 |
Osaka |
Josho Gakuen Osaka Center |
Considerations of a Common-mode Feedback Circuit in the CMOS Inverter-based Differential Amplifier. Masayuki Uno (Linear Cell Design) ICD2010-32 |
Push-pull CMOS inverter is effective for high-speed, low-power operations, but it has poor CMRR and PSRR characteristics... [more] |
ICD2010-32 pp.67-72 |
ICD, ITE-IST |
2010-07-23 10:30 |
Osaka |
Josho Gakuen Osaka Center |
The Design of a Highly Linearized Gm Amplifier by Adopting the Positive Feedback Compensation Scheme and its Application to High-Frequency Filters Yusuke Shimoyama, Yasuhiro Sugimoto (Chuo Univ.) ICD2010-33 |
In order to alleviate the design criteria such that the input dynamic range becomes small and that the amplifier gain ca... [more] |
ICD2010-33 pp.73-78 |
ICD, ITE-IST |
2010-07-23 11:05 |
Osaka |
Josho Gakuen Osaka Center |
On-chip background calibration of time-interleaved ADC Takashi Oshima, Tomomi Takahashi (Hitachi) ICD2010-34 |
An extremely-high-speed high-resolution time-interleaved ADC is a key enabler of the next-generation applications. The g... [more] |
ICD2010-34 pp.79-84 |
ICD, ITE-IST |
2010-07-23 11:30 |
Osaka |
Josho Gakuen Osaka Center |
A/D converter for CMOS Image Sensor with a variable gain amplifier features Tetsuya Iida, Tomoyuki Akahori (BT), Mohd Amrallah Bin Mustafa, Keita Yasutomi, Shoji Kawahito (Shizuoka Univ.) |
[more] |
|
ICD, ITE-IST |
2010-07-23 11:55 |
Osaka |
Josho Gakuen Osaka Center |
Interleaved ramp wave generator for single slope ADC Yukinobu Makihara, Shin Muon, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.) |
[more] |
|
ICD, ITE-IST |
2010-07-23 13:20 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
An All-Digital and Scalable Time-Mode A/D Converter TAD
-- Challenge for Sensor Circuit Digitalization -- Takamoto Watanabe (DENSO) |
[more] |
|
ICD, ITE-IST |
2010-07-23 14:10 |
Osaka |
Josho Gakuen Osaka Center |
[Invited Talk]
TDC and SOI Radiation Image Sensor for Particle Physics Yasuo Arai (KEK IPNS) |
[more] |
|
ICD, ITE-IST |
2010-07-23 15:10 |
Osaka |
Josho Gakuen Osaka Center |
Low noise sensor signal readout circuits with a response time acceleration technique Mars Kamel, Shoji Kawahito (Shizuoka Univ.) |
[more] |
|
ICD, ITE-IST |
2010-07-23 15:35 |
Osaka |
Josho Gakuen Osaka Center |
Design and Development of Polarization-Analyzing Image Sensor using 65nm CMOS Process Sanshiro Shishido, Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, Jun Ohta (NAIST) |
[more] |
|