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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2008)
Search Results: Keywords 'from:2008-07-17 to:2008-07-17'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, SDM | 2008-07-17 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of the Different Nature of Interface Defect States on the NBTI and 1/f noise of High-k / Metal Gate pMOSFETs between (100) and (110) Crystal Orientations Motoyuki Sato, Yoshihiro Sugita, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji (Selete)  SDM2008-128 ICD2008-38 |
Using (110) substarate is one of promissing candidate for pMOSTET boost technology. (110) surface shows not only higher ... [more] | SDM2008-128 ICD2008-38 pp.1-6 |
| ICD, SDM | 2008-07-17 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Drain Current Fluctuation in High-k Dielectric p-MOSFETs
-- Effects of Single-Hole Capture/Emission by the Traps in High-k Dielectric -- Shigeki Kobayashi, Masumi Saitoh, Ken Uchida (Corporate RDC, Toshiba Corp.) SDM2008-129 ICD2008-39 |
Random telegraph noise (RTN) in scaled MOSFETs is one of the biggest concerns in the present and future LSIs. However, R... [more] | SDM2008-129 ICD2008-39 pp.7-10 |
| ICD, SDM | 2008-07-17 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of Vth Variation Utilizing HfSiOx for 45nm SRAM Gen Tsutsui, Kazuaki Tsunoda, Nayuta Kariya, Yutaka Akiyama, Tomohisa Abe, Shinya Maruyama, Tadashi Fukase, Mieko Suzuki, Yasushi Yamagata, Kiyotaka Imai (NECEL) SDM2008-130 ICD2008-40 |
[more] | SDM2008-130 ICD2008-40 pp.11-16 |
| ICD, SDM | 2008-07-17 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41 |
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] | SDM2008-131 ICD2008-41 pp.17-22 |
| ICD, SDM | 2008-07-17 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A small-delay defect detection technique for dependable LSIs Koichiro Noguchi, Koichi Nose (NEC), Toshinobu Ono (NECEL), Masayuki Mizuno (NEC) SDM2008-132 ICD2008-42 |
As continuous process scaling produces large-scale chips, small-delay defects become one of the major chip-reliability l... [more] | SDM2008-132 ICD2008-42 pp.23-28 |
| ICD, SDM | 2008-07-17 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Progress of compact model for CMOS circuit design
-- Performance of HiSIM model based on the surface potential model -- Tatsuya Ohguro (Hiroshima Univ./Toshiba), Mitiko Miura-Mattausch (Hiroshima Univ.) SDM2008-133 ICD2008-43 |
HiSIM model based on the surface potential model has been popular because the model can accurately simulate analog and R... [more] | SDM2008-133 ICD2008-43 pp.29-34 |
| ICD, SDM | 2008-07-17 13:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Super Chip Technology to Achieve Ultimate Integration Mitsumasa Koyanagi, Tetsu Tanaka (Tohoku Univ.) SDM2008-134 ICD2008-44 |
[more] | SDM2008-134 ICD2008-44 pp.35-40 |
| ICD, SDM | 2008-07-17 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Special Talk]
Present Status and Future Trend of Characteristic Variations in Scaled CMOS Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete), Kiyoshi Takeuchi, Takaaki Tsunomura (/MIRAI-Selete), Arifin T.Putra (Univ. of Tokyo), Akio Nishida, Shiro Kamohara (/MIRAI-Selete) SDM2008-135 ICD2008-45 |
The variability is one of the most critical issues for further miniaturization of MOS transistors. Although the variabi... [more] | SDM2008-135 ICD2008-45 pp.41-46 |
| ICD, SDM | 2008-07-17 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46 |
We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array ... [more] | SDM2008-136 ICD2008-46 pp.47-52 |
| ICD, SDM | 2008-07-17 15:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2008-137 ICD2008-47 |
[more] | SDM2008-137 ICD2008-47 pp.53-58 |
| ICD, SDM | 2008-07-17 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Co-design of CNT based devices and circuitry
-- How can CNT-based circuit overcome Si-CMOS? -- Shinobu Fujita (Toshiba RDC) SDM2008-138 ICD2008-48 |
Emerging devices using new materials (post-Si) are expected to replace Si-based MOSFET in future. This paper firstly cla... [more] | SDM2008-138 ICD2008-48 pp.59-64 |
| ICD, SDM | 2008-07-18 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study of high-Speed low-power system LSI for sub-threshold operation Makoto Tsurukubo, Shigeyoshi Watanabe (SIT) SDM2008-139 ICD2008-49 |
[more] | SDM2008-139 ICD2008-49 pp.65-70 |
| ICD, SDM | 2008-07-18 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Examination of Low-power system LSI architecture by Real time scheduling Yoshikazu Sato, Shigeyoshi Watanabe (SIT) SDM2008-140 ICD2008-50 |
Reduction of power consumption of system LSI with fixed priority scheduling has been described. Scheme of power supply f... [more] | SDM2008-140 ICD2008-50 pp.71-76 |
| ICD, SDM | 2008-07-18 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.) SDM2008-141 ICD2008-51 |
A sub-$\micro$s wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and... [more] | SDM2008-141 ICD2008-51 pp.77-82 |
| ICD, SDM | 2008-07-18 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
CMOS-based biomedical photonic devices Takashi Tokuda, Jun Ohta (NAIST) SDM2008-142 ICD2008-52 |
CMOS-based biomedical photonic devices especially for bio-implant applications are proposed and discussed. We describe (... [more] | SDM2008-142 ICD2008-52 pp.83-88 |
| ICD, SDM | 2008-07-18 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Problems and Prospect of 3D Integration using Wireless and Optical Interconnection Technologies Atsushi Iwata, Shin Yokoyama (Hiroshima Univ.) SDM2008-143 ICD2008-53 |
n 3-D integration technology which aims to enhance integration scale and performance, chip-to-chip interconnection is th... [more] | SDM2008-143 ICD2008-53 pp.89-94 |
| ICD, SDM | 2008-07-18 13:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
RF MEMS for Reconfigurable CMOS Radio Kazuya Masu (Tokyo Tech.) SDM2008-144 ICD2008-54 |
[more] | SDM2008-144 ICD2008-54 pp.95-96 |
| ICD, SDM | 2008-07-18 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
-- feasibility study of BiCS type FeRAM and MRAM -- Shigeyoshi Watanabe, Koichi Sugano, Shouto Tamai (Shonan Institute of Tech.) SDM2008-145 ICD2008-55 |
[more] | SDM2008-145 ICD2008-55 pp.97-102 |
| ICD, SDM | 2008-07-18 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fabrication of Ultra Shallow Junction and Improvement of Metal Gate High-k CMOS Performance by FSP-FLA (Flexibly-Shaped-Pulse Flash-Lamp-Annealing) Technology Takashi Onizawa, Shinichi Kato, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji (selete) SDM2008-146 ICD2008-56 |
We propose the suitable milli-second annealing (MSA) for metal/high-k device performance and ultra-shallow-junction (USJ... [more] | SDM2008-146 ICD2008-56 pp.103-108 |
| ICD, SDM | 2008-07-18 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of Tantalum Composition in TaCx/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL Masakazu Goto, Kosuke Tatsumura, Shigeru Kawanaka, Kazuaki Nakajima, Reika Ichihara, Yasuhito Yoshimizu, Hiroyuki Onoda, Koji Nagatomo, Toshiyuki Sasaki, Takashi Fukushima, Akiko Nomachi, Seiji Inumiya, Tomonori Aoyama, Masato Koyama, Yoshiaki Toyoshima (Toshiba Corp.) SDM2008-147 ICD2008-57 |
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge genera... [more] | SDM2008-147 ICD2008-57 pp.109-114 |
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