| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD |
2006-05-25
10:30 |
Hyogo |
Kobe University |
Circuits Technologies for Flexible Braille Sheet Display with Organic FETs and Plastic Actuators
Hiroshi Kawaguchi (Kobe Univ.), Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Takao Someya, Takayasu Sakurai (Univ. of Tokyo) |
[more] |
ICD2006-22
pp.1-6 |
| ICD |
2006-05-25
11:00 |
Hyogo |
Kobe University |
1/1.8” 6.4M pixel 60frame/s CMOS Image Sensor
Masaru Kikuchi, Satoshi Yoshihara (Sony), Ken Koseki (Sony LSI Design), Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano (Sony), Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima (Sony LSI Design), Tadashi Nakajima, Yoshiharu Kudo, Fumihiko Koga, Tetsuo Nomoto (Sony) |
[more] |
ICD2006-23
pp.7-11 |
| ICD |
2006-05-25
11:30 |
Hyogo |
Kobe University |
System-in-Silicon architecture and its application to a motion estimation engine
Kouichi Kumagai (SFT), Changqi Yang (Waseda Univ.), Hitoshi Izumino, Nobuyuki Narita, Keisuke Shinjo, Shin-ichi Iwashita, Yuji Nakaoka, Tomohiro Kawamura, Hideo Komabashiri, Tsukasa Minato, Atsushi Ambo, Takamasa Suzuki (SFT), Zhenyu Liu, Yang Song, Satoshi Goto (Waseda Univ.) |
“System-in-Silicon” technology has been developed including multi-chip integration technology with fine pitch micro-bump... [more] |
ICD2006-24
pp.13-17 |
| ICD |
2006-05-25
13:00 |
Hyogo |
Kobe University |
A 40GOPS 250mW Massively Parallel Processor Based on Matrix Architecture
-- A Very High Performance Processor IP for Mobile System-on-Chips --
Kiyoshi Nakata, Masami Nakajima, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten (Renesas) |
We have developed a massively parallel processor based on Matrix architecture. This architecture achieved 40GOPS of 16-b... [more] |
ICD2006-25
pp.19-23 |
| ICD |
2006-05-25
13:30 |
Hyogo |
Kobe University |
Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs
Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL) |
[more] |
ICD2006-26
pp.25-30 |
| ICD |
2006-05-25
14:00 |
Hyogo |
Kobe University |
High-Speed Transceiver Circuit for a Multiprocessor Server Using Over 1Tb/s Crossbar
Ryuichi Nishiyama, Souta Sakabayashi, Jun Yamada, Hiroyuki Adachi, Yutaka Mori (Fujitsu) |
[more] |
ICD2006-27
pp.31-35 |
| ICD |
2006-05-25
14:45 |
Hyogo |
Kobe University |
[Special Invited Talk]
Technological trend of advanced processsors pursuing high performance/watt
Kunio Uchiyama (Hitachi) |
Recently, power consumption is the most critical theme in developing various kinds of processors. Although increasing th... [more] |
ICD2006-28
pp.37-42 |
| ICD |
2006-05-25
15:45 |
Hyogo |
Kobe University |
[Special Invited Talk]
Deep Sub-100nm Design Challenges
Tohru Furuyama (Toshiba) |
(To be available after the conference date) [more] |
ICD2006-29
pp.43-48 |
| ICD |
2006-05-26
10:30 |
Hyogo |
Kobe University |
A Digital Input Controller for Audio Class-D Amplifiers with 100W 0.004% THD+N and 113dB DR
Toru Ido, Sonny Ishizuka (TIJ), Lars Risbo (TIDK), Fumitaka Aoyagi, Toshihiko Hamasaki (TIJ) |
[more] |
ICD2006-30
pp.49-54 |
| ICD |
2006-05-26
11:00 |
Hyogo |
Kobe University |
A 80/100 MS/s 76.3/70.1-dB SNDR ΔΣ ADC for digital TV receivers
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal LoRe, Masayuki Miyamoto (Sharp) |
A 4th-order switched-capacitor $\Delta\Sigma$ ADC with a 4-bits quantizer is designed for a low-power direct-conversion ... [more] |
ICD2006-31
pp.55-60 |
| ICD |
2006-05-26
11:30 |
Hyogo |
Kobe University |
A 30mW 12b 50MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS.
Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihede Ogawa (Sony LSI) |
[more] |
ICD2006-32
pp.61-64 |
| ICD |
2006-05-26
13:00 |
Hyogo |
Kobe University |
A PLL for a DVDx16 Write System with 63 Output Phases and 32ps
Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie (Matsushita) |
[more] |
ICD2006-33
pp.65-70 |
| ICD |
2006-05-26
13:30 |
Hyogo |
Kobe University |
A 0.03mm2 9mW Wide-Range Duty-Cycle-Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface
Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi (Matsushita Electric), Makoto Hattori (PSCST) |
[more] |
ICD2006-34
pp.71-75 |
| ICD |
2006-05-26
14:00 |
Hyogo |
Kobe University |
An 18mW, 90 to 770MHz Synthesizer with Agile Auto-Tuning for Digital TV-tuners
Masazumi Marutani, Hideaki Anbutsu, Masafumi Kondo, Noriaki Shirai, Hiroshi Yamazaki, Yuu Watanabe (Fujitsu) |
[more] |
ICD2006-35
pp.77-82 |
| ICD |
2006-05-26
14:45 |
Hyogo |
Kobe University |
1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications
Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe (Advantest) |
A high-speed, precise fully CMOS dynamic arbitrary timing generator for >4GHz automatic test equipment (ATE) application... [more] |
ICD2006-36
pp.83-87 |
| ICD |
2006-05-26
15:15 |
Hyogo |
Kobe University |
A 1-ps Resolution Jitter Measurement Macro Using Interpolated Jitter Oversampling
Koichi Nose, Mikihiro Kajita, Masayuki Mizuno (NEC) |
[more] |
ICD2006-37
pp.89-94 |
| ICD |
2006-05-26
15:45 |
Hyogo |
Kobe University |
A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu (Keio Univ.), Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi (NEC), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.) |
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate o... [more] |
ICD2006-38
pp.95-100 |
| ICD |
2006-05-26
16:15 |
Hyogo |
Kobe University |
A 20Gb/s Bidirectional Transceiver Using a Resister-Transconductor Hybrid
Yasumoto Tomita (Keio Univ.), Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh (Fujitsu Laboratories LTD.), Tadahiro Kuroda (Keio Univ.) |
This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in a ... [more] |
ICD2006-39
pp.101-104 |
|