| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD |
2006-04-13
09:20 |
Oita |
Oita University |
The Origin of Variable Retention Time in DRAM
-- Fluctuation of Junction Leakage --
Yuki Mori (Hitachi CRL), Kiyonori Ohyu, Kensuke Okonogi (Elpida), Renichi Yamada (Hitachi CRL) |
[more] |
ICD2006-1
pp.1-6 |
| ICD |
2006-04-13
09:45 |
Oita |
Oita University |
A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode
Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba) |
An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM... [more] |
ICD2006-2
pp.7-12 |
| ICD |
2006-04-13
10:10 |
Oita |
Oita University |
An 8.4ns Column-Access 1.6Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme
Shuichi Kubouchi (Hitachi ULSI), Hiroki Fujisawa, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda (Elpida Memory), Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka (Hitachi ULSI), Masayuki Nakamura (Elpida Memory) |
The column access time of a 512Mb DDR3 SDRAM made by a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through ... [more] |
ICD2006-3
pp.13-18 |
| ICD |
2006-04-13
10:45 |
Oita |
Oita University |
[Special Invited Talk]
Sub-1V DRAM Design
Takayuki Kawahara (Hitachi Central Research Lab.) |
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,... [more] |
ICD2006-4
pp.19-24 |
| ICD |
2006-04-13
11:35 |
Oita |
Oita University |
Technology development of 128Mb-FBC(Floating Body Cell) Memory by 90nm node CMOS process
Hiroomi Nakajima, Yoshihiro Minami, Tomoaki Shino (SoC Center, Toshiba), Atsushi Sakamoto (TJ), Tomoki Higashi (TOSMEC), Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama (SoC Center, Toshiba) |
A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. In order to realize f... [more] |
ICD2006-5
pp.25-30 |
| ICD |
2006-04-13
13:00 |
Oita |
Oita University |
[Special Invited Talk]
Techniques and Scaling Scenario for Chain FeRAM
Daisaburo Takashima (Toshiba) |
A chain FeRAM architecture is the best solution to realize high-density, high-speed and low power nonvolatile memory. In... [more] |
ICD2006-6
pp.31-36 |
| ICD |
2006-04-13
13:50 |
Oita |
Oita University |
[Special Invited Talk]
A Metal-Oxide Resistance Changing type NVM Technology
Masao Taguchi (Spansion) |
Abstract A non-volatile-memory technology so called ReRAM which utilizes electrical switching behavior of a thin insula... [more] |
|
| ICD |
2006-04-13
14:50 |
Oita |
Oita University |
[Special Invited Talk]
New Memory Device on SoC Platform
Kazutami Arimoto (Renesas) |
Advanced SoC platform which is based on open architecture consists of hardware/ software interconnection and scalable c... [more] |
ICD2006-7
pp.37-42 |
| ICD |
2006-04-13
15:40 |
Oita |
Oita University |
[Special Invited Talk]
Requirement for the Memory Architecture from the SoC Design Point of View
Masafumi Takahashi (Toshiba) |
[more] |
ICD2006-8
pp.43-48 |
| ICD |
2006-04-13
16:40 |
Oita |
Oita University |
[Panel Discussion]
What is your urgent task in R/D of new embedded memories?
Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba) |
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] |
ICD2006-9
p.49 |
| ICD |
2006-04-14
08:40 |
Oita |
Oita University |
Nonvolatile SRAM based on Phase Change
Masashi Takata, Kazuya Nakayama, Takatomi Izumi, Toru Shinmura, Junichi Akita, Akio Kitagawa (Kanazawa Univ.) |
[more] |
ICD2006-10
pp.51-56 |
| ICD |
2006-04-14
09:05 |
Oita |
Oita University |
Pipelined Self Reference Read Scheme for MRAM
Leona Okamura (Waseda Univ.), Yuji Kihara (Renesas Technology Inc.), Kim Tae Yun, Fuminori Kimura, Yusuke Matsui (Waseda Univ.), Tsukasa Oishi (Renesas Technology Inc.), Tsutomu Yoshihara (Waseda Univ.) |
[more] |
ICD2006-11
pp.57-62 |
| ICD |
2006-04-14
09:30 |
Oita |
Oita University |
a 4Mb MRAM and its experimental application
Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Kiyokazu Nagahara, Sadahiko Miura, Ken-ichi Shimura, Kiyotaka Tsuji, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Yuko Kato, Shinsaku Saito, Naoki Kasai, Hideaki Numata, Norikazu Ohshima (NEC) |
The memory-cell technology, circuit technology and fabrication results of a newly developed 4Mb MRAM and an application ... [more] |
ICD2006-12
pp.63-67 |
| ICD |
2006-04-14
09:55 |
Oita |
Oita University |
High Performance 16Mb MRAM for Portable Applications
Yuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Ryosuke Takizawa, Yoshihiro Ueda, Kiyotaro Itagaki, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, Masahiko Nakayama, Hiroaki Yoda (Toshiba Co.) |
[more] |
ICD2006-13
pp.69-73 |
| ICD |
2006-04-14
10:25 |
Oita |
Oita University |
[Special Invited Talk]
Spin-Transfer Torque Writing Technology (STT-RAM) For Future MRAM
Hide Nagai, Yiming Huai (Grandis), Shuichi Ueno, Tsuyoshi Koga (Renesas Technology) |
[more] |
ICD2006-14
pp.75-80 |
| ICD |
2006-04-14
11:15 |
Oita |
Oita University |
DRAM技術を用いた16M SRAM
Yuji Kihara, Yasushi Nakashima, Takashi Izutsu, Masayuki Nakamoto (Renesas), Tsutomu Yoshihara (Waseda Univ.) |
A 16Mbit Low Power SRAM with 0.98um2 cells using 0.15um DRAM and TFT technology has been developed. A new type memory ce... [more] |
ICD2006-15
pp.81-84 |
| ICD |
2006-04-14
11:40 |
Oita |
Oita University |
Redefinition of Write Margin for Next-Generation SRAMs and Write-Margin Monitoring Circuits
Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura (NEC), Hiroyuki Kobatake (NECEL) |
[more] |
ICD2006-16
pp.85-90 |
| ICD |
2006-04-14
13:00 |
Oita |
Oita University |
[Special Invited Talk]
Low-Power Low-Voltage SRAM Design for Battery Operation
Masanao Yamaoka (Hitachi, Ltd.) |
In the processors for mobile devices, the power consumption
of the embedded SRAMs has large impact on the total power c... [more] |
ICD2006-17
pp.91-96 |
| ICD |
2006-04-14
13:50 |
Oita |
Oita University |
Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability
Yasumasa Tsukamoto, Koji Nii (Renesas Technology), Susumu Imaoka (Renesas Design), Yuji Oda (Shikino High-Tech.), Shigeki Ohbayashi, Makoto Yabuuchi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
[more] |
ICD2006-18
pp.97-102 |
| ICD |
2006-04-14
14:20 |
Oita |
Oita University |
Floating Gate Type Planar MOSFET Memory with 35 nm Gate Length using Double Junction Tunneling
Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba) |
[more] |
ICD2006-19
pp.103-107 |
|