| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD |
2005-05-26
10:00 |
Hyogo |
Kobe Univ. |
A Low-power Systolic Array Architecture for Block-matching Motion Estimation
Junichi Miyakoshi, Yuichiro Murachi (Kobe Univ.), Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto (Kanazawa Univ.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-20
pp.1-6 |
| ICD |
2005-05-26
10:30 |
Hyogo |
Kobe Univ. |
A Single-Chip Multi-Processor integrating Quadruple Processors on 90nm CMOS Process
Ken-ichi Kawasaki, Tetsuyoshi Shiota, Yukihito Kawabe, Wataru Shibamoto, Atsushi Sato, Tetsutaro Hashimoto, Motoaki Matsumura, Hiroshi Okano, Fumihiko Hayakawa, Shinichiro Tago, Yasuki Nakamura (Fujitsu Labs.), Hideo Miyake (FLT), Atsuhiro Suga, Hiromasa Takahashi, Atsuki Inoue (Fujitsu Labs.) |
We have developed a 51.2-GOPS single-chip multi-processor integrating quadruple processors with 1.0-GB/s system-bus dire... [more] |
ICD2005-21
pp.7-12 |
| ICD |
2005-05-26
11:00 |
Hyogo |
Kobe Univ. |
An H.264/MPEG-4 Audio/Visual Codec LSI with Module-Wise Dynamic Voltage/Frequency Scaling
Yoshiyuki Kitasho, Toshihide Fujiyoshi, Shinichiro Shiratake, Tsuyoshi Nishikawa, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Masafumi Takahashi, Yukihito Oowaki (TOSHIBA) |
A single-chip MPEG-4 audiovisual LSI with ability of CIF 15fps encoding is fabricated in a 0.13um CMOS, 5-layer metal te... [more] |
ICD2005-22
pp.13-18 |
| ICD |
2005-05-26
11:30 |
Hyogo |
Kobe Univ. |
A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-line and Double Bit-line Structure
Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai (Univ. of Tokyo) |
Double word-line and bit-line structure in an organic FET-based sheet-type scanner is described. This structure reduces ... [more] |
ICD2005-23
pp.19-21 |
| ICD |
2005-05-26
13:00 |
Hyogo |
Kobe Univ. |
A Loop-Bandwidth Calibration System for Fractional-N Synthesizer and ΔΣ PLL Transmitter
Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki (Hitachi), Nigel Tolson (RTE), Masumi Kasahara (Renesas), Satoshi Tanaka (Hitachi) |
In this presentation, we propose a new calibration method for loop gain of a delta-sigma PLL transmitter, that can tune ... [more] |
ICD2005-24
pp.23-28 |
| ICD |
2005-05-26
13:30 |
Hyogo |
Kobe Univ. |
A 1.2V 3.5mW Delta-Sigma Modulator with a Passive Current Summing Network and a Variable Gain Function
Toshiaki Nagai, Hiroyuki Satou, Hiroshi Yamazaki, Yuu Watanabe (Fujitsu Ltd.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-25
pp.29-33 |
| ICD |
2005-05-26
14:00 |
Hyogo |
Kobe Univ. |
A CMOS Rotary Encoder System Based on Magnetic Pattern Analysis with a Resolution of 10b per Rotation
Kazuhiro Nakano (Shizuoka Univ.), Toru Takahashi, Yoshitaka Nagano (NTN), Shoji Kawahito (Shizuoka Univ.) |
This paper presents a single-chip CMOS magnetic rotary encoder system based on magnetic pattern analysis. A rotary encod... [more] |
ICD2005-26
pp.35-40 |
| ICD |
2005-05-26
14:30 |
Hyogo |
Kobe Univ. |
A 19.5b Wide Dynamic Range CMOS Image Sensor with 12b Column-Parallel Cyclic A/D Converters
Masaaki Sasaki (Sendai National College of Tech.), Mitsuhito Mase (Shizuoka Univ.), Shoji Kawahito (Research Institute of Elec., Shizuoka Univ.), Yasuo Wakamori (Yamaha) |
A wide dynamic range CMOS image sensor with burst readout multiple exposure is proposed. In this method, maximaly four d... [more] |
ICD2005-27
pp.41-46 |
| ICD |
2005-05-27
10:00 |
Hyogo |
Kobe Univ. |
A 10-Gb/s Burst-Mode CDR IC in 0.13-um CMOS
Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki, Yusuke Ohtomo (NTT) |
A 10-Gb/s burst-mode CDR IC was fabricated in a 0.13-$\mu$m CMOS process for the high-speed packet-based networks of the... [more] |
ICD2005-28
pp.1-5 |
| ICD |
2005-05-27
10:30 |
Hyogo |
Kobe Univ. |
1.25Gb/s Burst-Mode Receiver ICs with Quick Response for PON systems
Makoto Nakamura, Yuhki Imai, Yohtaro Umeda, Jun Endo, Yuji Akatsu (NTT) |
We have developed 1.25-Gbit/s burst-mode receiver ICs for optical access networks. We devised a quick-response receiver ... [more] |
ICD2005-29
pp.7-11 |
| ICD |
2005-05-27
11:00 |
Hyogo |
Kobe Univ. |
12Gb/s duobinary signaling with x2 oversampled edge equalization
Kouichi Yamaguchi, Kazuhisa Sunaga, Shunichi Kaeriyama, Takaaki Nedachi, Makoto Takamiya, Koichi Nose, Yoshihiro Nakagawa (NEC), Mitsutoshi Sugawara (NEC-EL America), Muneo Fukaishi (NEC) |
A backplane transceiver in 90nm CMOS that employs duobinary signaling over copper traces is described. To introduce duob... [more] |
ICD2005-30
pp.13-18 |
| ICD |
2005-05-27
11:30 |
Hyogo |
Kobe Univ. |
A 950MHz Rectifier Circuit for Sensor Networks with 10m Distance
Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka (TOSHIBA) |
This paper presents a wireless power transmission system and a high-sensitivity rectifier circuit for ubiquitous sensor ... [more] |
ICD2005-31
pp.19-24 |
| ICD |
2005-05-27
13:00 |
Hyogo |
Kobe Univ. |
A Single-Chip Si-LDMOS Power Amplifier for GSM
Toshihiko Shimizu, Yoshikuni Matsunaga, Satoshi Sakurai (Renesas), Isao Yoshida (ATN), Masao Hotta (Musashi Inst. of Tech.) |
A single-chip Si-LDMOS high-power amplifier with matching circuits and all control blocks for quad-band GSM handset phon... [more] |
ICD2005-32
pp.25-29 |
| ICD |
2005-05-27
13:30 |
Hyogo |
Kobe Univ. |
Integrated stereo sigma-delta class D amplifier
Eric Gaalaas (ADI), Bill Liu, Naoaki Nishimura (ADKK) |
(Advance abstract in Japanese is available) [more] |
ICD2005-33
pp.31-34 |
| ICD |
2005-05-27
14:00 |
Hyogo |
Kobe Univ. |
A 0.18um 102dB-SNR Mixed CT SC Audio-Band delta-sigma ADC
Paul Morrow, Maria Chamarro, Colin Lyden, Pablo Ventura (Analog Devices), Andrew Abo (Telegent Systems), Atsushi Matamura, Mike-D Keane, Richard O'Brien, Niall McGuinness, Paschal Minogue, Martin McGranaghan, Johan Mansson, Ivan Ryan (Analog Devices) |
(Advance abstract in Japanese is available) [more] |
ICD2005-34
pp.35-38 |
| ICD |
2005-05-27
14:30 |
Hyogo |
Kobe Univ. |
Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL controlled by Delta-Sigma Modulator with Level Shifter
Takashi Kawamoto, Masaru Kokubo, Takashi Oshima (Hitachi Ltd), Takayuki Noto, Masato Suzuki, Shigeyuki Suzuki, Takashi Hayasaka, Tomoaki Takahashi, Jun Kasai (Renesas Technology Corp.) |
The spread spectrum clock generator (SSCG) for Serial ATA with a new architecture is fabricated in a 0.15um CMOS process... [more] |
ICD2005-35
pp.39-44 |
| ICD |
2005-05-27
15:10 |
Hyogo |
Kobe Univ. |
A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue (Keio Univ.), Takayasu Sakurai (Univ. of Tokyo), Tadahiro Kuroda (Keio Univ.) |
A wireless interface by inductive coupling achieves aggregate data rate of 195Gb/s among 4 stacked chips in a package by... [more] |
ICD2005-36
pp.45-50 |
| ICD |
2005-05-27
15:40 |
Hyogo |
Kobe Univ. |
A 3D-Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains
Atsushi Iwata, Mamoru Sasaki, Takamaro Kikkawa, Seiji Kameda, Hiroshi Ando, Kentaro Kimoto, Daisuke Arizono, Hideo Sunami (Hiroshima Univ.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-37
pp.51-56 |
| ICD |
2005-05-27
16:10 |
Hyogo |
Kobe Univ. |
A Programmable On-Chip Picosecond Jitter Measurement Circuit without a Reference Clock
Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi (Advantest Labs.), Mani Soma (Univ. of Washington), Masakatsu Suda, Toshiyuki Okayasu, Daisuke Watanabe, Kazuhiro Yamamoto (Advantest) |
A new on-chip jitter measurement circuit, which does not require a reference clock, is proposed. It consists of a combin... [more] |
ICD2005-38
pp.57-60 |
| ICD |
2005-05-27
16:40 |
Hyogo |
Kobe Univ. |
Substrate Integrity Beyond 1GHz
Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.), Naoyuki Hamanishi, Masazumi Shiochi, Tetsuya Iida (Toshiba Corp.), Junichiro Watanabe (Toshiba Information Systems(Japan) Corp.), Yoshitaka Murasaka, Atsushi Iwata (A-R-Tec Corp.) |
(Advance abstract in Japanese is available) [more] |
ICD2005-39
pp.61-64 |